diff options
Diffstat (limited to 'llvm/test/MC/ARM/invalid-neon-v8.s')
| -rw-r--r-- | llvm/test/MC/ARM/invalid-neon-v8.s | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/llvm/test/MC/ARM/invalid-neon-v8.s b/llvm/test/MC/ARM/invalid-neon-v8.s index 361946d4a07..fdff360abb2 100644 --- a/llvm/test/MC/ARM/invalid-neon-v8.s +++ b/llvm/test/MC/ARM/invalid-neon-v8.s @@ -1,9 +1,9 @@ @ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s vmaxnm.f32 s4, d5, q1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction vmaxnm.f64.f64 s4, d5, q1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction vmaxnmge.f64.f64 s4, d5, q1 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified @@ -12,16 +12,20 @@ vcvta.s32.f32 s1, s2 vcvtp.u32.f32 s1, d2 @ CHECK: error: invalid operand for instruction vcvtp.f32.u32 d1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction vcvtplo.f32.u32 s1, s2 @ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified vrinta.f64.f64 s3, d12 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction vrintn.f32 d3, q12 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: note: invalid operand for instruction +@ CHECK: note: invalid operand for instruction vrintz.f32 d3, q12 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: note: invalid operand for instruction +@ CHECK: note: invalid operand for instruction vrintmge.f32.f32 d3, d4 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified @@ -46,7 +50,7 @@ sha1heq.32 q0, q1 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified sha1c.32 s0, d1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction sha1m.32 q0, s1, q2 @ CHECK: error: invalid operand for instruction sha1p.32 s0, q1, q2 @@ -58,12 +62,12 @@ sha256h.32 q0, s1, q2 sha256h2.32 q0, q1, s2 @ CHECK: error: invalid operand for instruction sha256su1.32 s0, d1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction sha256su1lt.32 q0, d1, q2 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified vmull.p64 q0, s1, s3 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid instruction vmull.p64 s1, d2, d3 @ CHECK: error: invalid operand for instruction vmullge.p64 q0, d16, d17 |
