diff options
Diffstat (limited to 'llvm/test/MC/ARM/invalid-neon-v8.s')
| -rw-r--r-- | llvm/test/MC/ARM/invalid-neon-v8.s | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/llvm/test/MC/ARM/invalid-neon-v8.s b/llvm/test/MC/ARM/invalid-neon-v8.s index fdff360abb2..6403904c1d3 100644 --- a/llvm/test/MC/ARM/invalid-neon-v8.s +++ b/llvm/test/MC/ARM/invalid-neon-v8.s @@ -10,7 +10,7 @@ vmaxnmge.f64.f64 s4, d5, q1 vcvta.s32.f32 s1, s2 @ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f32 s1, d2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [d0, d31] vcvtp.f32.u32 d1, q2 @ CHECK: error: invalid instruction vcvtplo.f32.u32 s1, s2 @@ -20,47 +20,47 @@ vrinta.f64.f64 s3, d12 @ CHECK: error: invalid instruction vrintn.f32 d3, q12 @ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: invalid operand for instruction -@ CHECK: note: invalid operand for instruction +@ CHECK: note: operand must be a register in range [d0, d31] +@ CHECK: note: operand must be a register in range [q0, q15] vrintz.f32 d3, q12 @ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: invalid operand for instruction -@ CHECK: note: invalid operand for instruction +@ CHECK: note: operand must be a register in range [d0, d31] +@ CHECK: note: operand must be a register in range [q0, q15] vrintmge.f32.f32 d3, d4 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified aesd.8 q0, s1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] aese.8 s0, q1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] aesimc.8 s0, q1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] aesmc.8 q0, d1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] aesdge.8 q0, q1 @ CHECK: error: instruction 'aesd' is not predicable, but condition code specified sha1h.32 d0, q1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha1su1.32 q0, s1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha256su0.32 s0, q1 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha1heq.32 q0, q1 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified sha1c.32 s0, d1, q2 @ CHECK: error: invalid instruction sha1m.32 q0, s1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha1p.32 s0, q1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha1su0.32 d0, q1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha256h.32 q0, s1, q2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha256h2.32 q0, q1, s2 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] sha256su1.32 s0, d1, q2 @ CHECK: error: invalid instruction sha256su1lt.32 q0, d1, q2 @@ -69,6 +69,6 @@ sha256su1lt.32 q0, d1, q2 vmull.p64 q0, s1, s3 @ CHECK: error: invalid instruction vmull.p64 s1, d2, d3 -@ CHECK: error: invalid operand for instruction +@ CHECK: error: operand must be a register in range [q0, q15] vmullge.p64 q0, d16, d17 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified |
