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-rw-r--r--llvm/test/MC/ARM/invalid-fp-armv8.s10
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/test/MC/ARM/invalid-fp-armv8.s b/llvm/test/MC/ARM/invalid-fp-armv8.s
index d295ffeb7f3..da952cf7ed6 100644
--- a/llvm/test/MC/ARM/invalid-fp-armv8.s
+++ b/llvm/test/MC/ARM/invalid-fp-armv8.s
@@ -57,22 +57,26 @@ vmaxnmgt.f64 q0, s3, q1
vcvta.s32.f64 d3, s2
@ V8: error: invalid instruction
vcvtp.s32.f32 d3, s2
-@ V8: error: invalid operand for instruction
+@ V8: error: operand must be a register in range [s0, s31]
vcvtn.u32.f64 d3, s2
@ V8: error: invalid instruction
vcvtm.u32.f32 d3, s2
-@ V8: error: invalid operand for instruction
+@ V8: error: operand must be a register in range [s0, s31]
vcvtnge.u32.f64 d3, s2
@ V8: error: instruction 'vcvtn' is not predicable, but condition code specified
vcvtbgt.f64.f16 q0, d3
@ V8: error: invalid instruction
vcvttlt.f64.f16 s0, s3
+@ V8: error: invalid instruction, any one of the following would fix this:
+@ V8: note: operand must be a register in range [d0, d31]
@ V8: note: invalid operand for instruction
vcvttvs.f16.f64 s0, s3
+@ V8: error: invalid instruction, any one of the following would fix this:
+@ V8: note: operand must be a register in range [d0, d31]
@ V8: note: invalid operand for instruction
vcvtthi.f16.f64 q0, d3
-@ V8: error: invalid operand for instruction
+@ V8: error: operand must be a register in range [s0, s31]
vrintrlo.f32.f32 d3, q0
@ V8: error: invalid instruction
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