diff options
Diffstat (limited to 'llvm/test/CodeGen')
5 files changed, 326 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll new file mode 100644 index 00000000000..30b502ec6e9 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll @@ -0,0 +1,103 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s + +; TODO: Merge with DAG test + +define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) { +; CI-LABEL: is_private_vgpr: +; CI: ; %bb.0: +; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; CI-NEXT: v_mul_lo_u32 v2, 0, v0 +; CI-NEXT: v_mul_lo_u32 v1, 8, v1 +; CI-NEXT: v_mul_lo_u32 v3, 8, v0 +; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; CI-NEXT: v_mul_hi_u32 v0, 8, v0 +; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v0 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v3 +; CI-NEXT: v_mov_b32_e32 v2, s1 +; CI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; CI-NEXT: s_load_dword s0, s[4:5], 0x11 +; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 +; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: s_endpgm +; +; GFX9-LABEL: is_private_vgpr: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 +; GFX9-NEXT: v_mul_lo_u32 v1, 8, v1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; GFX9-NEXT: v_mul_hi_u32 v3, 8, v0 +; GFX9-NEXT: v_mul_lo_u32 v0, 8, v0 +; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 +; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) +; GFX9-NEXT: s_lshl_b32 s0, s0, 16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-NEXT: global_store_dword v[0:1], v0, off +; GFX9-NEXT: s_endpgm + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id + %ptr = load volatile i8*, i8* addrspace(1)* %gep + %val = call i1 @llvm.amdgcn.is.private(i8* %ptr) + %ext = zext i1 %val to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + +define amdgpu_kernel void @is_private_sgpr(i8* %ptr) { +; CI-LABEL: is_private_sgpr: +; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_load_dword s0, s[4:5], 0x11 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_cmp_eq_u32 s1, s0 +; CI-NEXT: s_cbranch_scc0 BB1_2 +; CI-NEXT: ; %bb.1: ; %bb0 +; CI-NEXT: v_mov_b32_e32 v0, 0 +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: BB1_2: ; %bb1 +; CI-NEXT: s_endpgm +; +; GFX9-LABEL: is_private_sgpr: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) +; GFX9-NEXT: s_lshl_b32 s0, s0, 16 +; GFX9-NEXT: s_cmp_eq_u32 s1, s0 +; GFX9-NEXT: s_cbranch_scc0 BB1_2 +; GFX9-NEXT: ; %bb.1: ; %bb0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_store_dword v[0:1], v0, off +; GFX9-NEXT: BB1_2: ; %bb1 +; GFX9-NEXT: s_endpgm + %val = call i1 @llvm.amdgcn.is.private(i8* %ptr) + br i1 %val, label %bb0, label %bb1 + +bb0: + store volatile i32 0, i32 addrspace(1)* undef + br label %bb1 + +bb1: + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i1 @llvm.amdgcn.is.private(i8* nocapture) #0 + +attributes #0 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll new file mode 100644 index 00000000000..1b4ce58041e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll @@ -0,0 +1,103 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s + +; TODO: Merge with DAG test + +define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { +; CI-LABEL: is_local_vgpr: +; CI: ; %bb.0: +; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; CI-NEXT: v_mul_lo_u32 v2, 0, v0 +; CI-NEXT: v_mul_lo_u32 v1, 8, v1 +; CI-NEXT: v_mul_lo_u32 v3, 8, v0 +; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; CI-NEXT: v_mul_hi_u32 v0, 8, v0 +; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v0 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v3 +; CI-NEXT: v_mov_b32_e32 v2, s1 +; CI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; CI-NEXT: s_load_dword s0, s[4:5], 0x10 +; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 +; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: s_endpgm +; +; GFX9-LABEL: is_local_vgpr: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 +; GFX9-NEXT: v_mul_lo_u32 v1, 8, v1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; GFX9-NEXT: v_mul_hi_u32 v3, 8, v0 +; GFX9-NEXT: v_mul_lo_u32 v0, 8, v0 +; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 +; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9-NEXT: s_lshl_b32 s0, s0, 16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-NEXT: global_store_dword v[0:1], v0, off +; GFX9-NEXT: s_endpgm + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id + %ptr = load volatile i8*, i8* addrspace(1)* %gep + %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) + %ext = zext i1 %val to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + +define amdgpu_kernel void @is_local_sgpr(i8* %ptr) { +; CI-LABEL: is_local_sgpr: +; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_load_dword s0, s[4:5], 0x10 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_cmp_eq_u32 s1, s0 +; CI-NEXT: s_cbranch_scc0 BB1_2 +; CI-NEXT: ; %bb.1: ; %bb0 +; CI-NEXT: v_mov_b32_e32 v0, 0 +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: BB1_2: ; %bb1 +; CI-NEXT: s_endpgm +; +; GFX9-LABEL: is_local_sgpr: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9-NEXT: s_lshl_b32 s0, s0, 16 +; GFX9-NEXT: s_cmp_eq_u32 s1, s0 +; GFX9-NEXT: s_cbranch_scc0 BB1_2 +; GFX9-NEXT: ; %bb.1: ; %bb0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_store_dword v[0:1], v0, off +; GFX9-NEXT: BB1_2: ; %bb1 +; GFX9-NEXT: s_endpgm + %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) + br i1 %val, label %bb0, label %bb1 + +bb0: + store volatile i32 0, i32 addrspace(1)* undef + br label %bb1 + +bb1: + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0 + +attributes #0 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll index 5a9d72d36be..7efd007195e 100644 --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -12,6 +12,9 @@ declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 +declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #2 +declare i1 @llvm.amdgcn.is.private(i8* nocapture) #2 + ; HSA: define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { %val = call i32 @llvm.amdgcn.workgroup.id.x() @@ -231,6 +234,22 @@ define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 { ret void } +; HSA: define amdgpu_kernel void @use_is_shared(i8* %ptr) #11 { +define amdgpu_kernel void @use_is_shared(i8* %ptr) #1 { + %is.shared = call i1 @llvm.amdgcn.is.shared(i8* %ptr) + %ext = zext i1 %is.shared to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + +; HSA: define amdgpu_kernel void @use_is_private(i8* %ptr) #11 { +define amdgpu_kernel void @use_is_private(i8* %ptr) #1 { + %is.private = call i1 @llvm.amdgcn.is.private(i8* %ptr) + %ext = zext i1 %is.private to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll new file mode 100644 index 00000000000..f324ba98ebe --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll @@ -0,0 +1,50 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s + +; GCN-LABEL: {{^}}is_private_vgpr: +; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]{{\]}} +; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11 +; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) +; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 +; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]] +; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc +define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id + %ptr = load volatile i8*, i8* addrspace(1)* %gep + %val = call i1 @llvm.amdgcn.is.private(i8* %ptr) + %ext = zext i1 %val to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + +; FIXME: setcc (zero_extend (setcc)), 1) not folded out, resulting in +; select and vcc branch. + +; GCN-LABEL: {{^}}is_private_sgpr: +; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} +; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) + +; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}} +; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}} +; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 + +; GCN: v_mov_b32_e32 [[V_APERTURE:v[0-9]+]], [[APERTURE]] +; GCN: v_cmp_eq_u32_e32 vcc, [[PTR_HI]], [[V_APERTURE]] +; GCN: s_cbranch_vccnz +define amdgpu_kernel void @is_private_sgpr(i8* %ptr) { + %val = call i1 @llvm.amdgcn.is.private(i8* %ptr) + br i1 %val, label %bb0, label %bb1 + +bb0: + store volatile i32 0, i32 addrspace(1)* undef + br label %bb1 + +bb1: + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i1 @llvm.amdgcn.is.private(i8* nocapture) #0 + +attributes #0 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll new file mode 100644 index 00000000000..1371392eb0a --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll @@ -0,0 +1,51 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s + +; GCN-LABEL: {{^}}is_local_vgpr: +; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]{{\]}} +; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 +; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 + +; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]] +; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc +define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id + %ptr = load volatile i8*, i8* addrspace(1)* %gep + %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) + %ext = zext i1 %val to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + +; FIXME: setcc (zero_extend (setcc)), 1) not folded out, resulting in +; select and vcc branch. + +; GCN-LABEL: {{^}}is_local_sgpr: +; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} +; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9-DAG: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 + +; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}} +; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}} + +; GCN: v_mov_b32_e32 [[V_APERTURE:v[0-9]+]], [[APERTURE]] +; GCN: v_cmp_eq_u32_e32 vcc, [[PTR_HI]], [[V_APERTURE]] +; GCN: s_cbranch_vccnz +define amdgpu_kernel void @is_local_sgpr(i8* %ptr) { + %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) + br i1 %val, label %bb0, label %bb1 + +bb0: + store volatile i32 0, i32 addrspace(1)* undef + br label %bb1 + +bb1: + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0 + +attributes #0 = { nounwind readnone speculatable } |
