3 files changed, 72 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Nios2/add-sub.ll b/llvm/test/CodeGen/Nios2/add-sub.ll
new file mode 100644
index 00000000000..7c9a2896ed9
--- /dev/null
+++ b/llvm/test/CodeGen/Nios2/add-sub.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
+; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
+
+define i32 @add_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: add_reg:
+; CHECK:   add r2, r4, r5
+  %c = add i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @sub_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: sub_reg:
+; CHECK:   sub r2, r4, r5
+  %c = sub i32 %a, %b
+  ret i32 %c
+}
+
diff --git a/llvm/test/CodeGen/Nios2/mul-div.ll b/llvm/test/CodeGen/Nios2/mul-div.ll
new file mode 100644
index 00000000000..8327823cf14
--- /dev/null
+++ b/llvm/test/CodeGen/Nios2/mul-div.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
+; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
+
+define i32 @mul_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: mul_reg:
+; CHECK:   mul r2, r4, r5
+  %c = mul i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @div_signed(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: div_signed:
+; CHECK:   div r2, r4, r5
+  %c = sdiv i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @div_unsigned(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: div_unsigned:
+; CHECK:   divu r2, r4, r5
+  %c = udiv i32 %a, %b
+  ret i32 %c
+}
+
diff --git a/llvm/test/CodeGen/Nios2/shift-rotate.ll b/llvm/test/CodeGen/Nios2/shift-rotate.ll
new file mode 100644
index 00000000000..d3084b5fb59
--- /dev/null
+++ b/llvm/test/CodeGen/Nios2/shift-rotate.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
+; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
+
+define i32 @sll_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: sll_reg:
+; CHECK:   sll r2, r4, r5
+  %c = shl i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @srl_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: srl_reg:
+; CHECK:   srl r2, r4, r5
+  %c = lshr i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @sra_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: sra_reg:
+; CHECK:   sra r2, r4, r5
+  %c = ashr i32 %a, %b
+  ret i32 %c
+}