diff options
Diffstat (limited to 'llvm/test/CodeGen')
23 files changed, 47 insertions, 42 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll index 1fb386cd4cd..b0ee7f323f3 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -441,7 +441,7 @@ endif: ; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]] ; GCN-NEXT: ; mask branch [[RET:BB[0-9]+_[0-9]+]] -; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop_body +; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop ; GCN: ;;#ASMSTART ; GCN: v_nop_e64 ; GCN: v_nop_e64 @@ -452,7 +452,7 @@ endif: ; GCN: ;;#ASMEND ; GCN: s_cbranch_vccz [[RET]] -; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop_body +; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop ; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1 ; GCN-NEXT: s_getpc_b64 vcc ; GCN-NEXT: s_sub_u32 vcc_lo, vcc_lo, ([[LONGBB]]+4)-[[LOOP_BODY]] diff --git a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll index e198abf77d1..8489a785310 100644 --- a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll +++ b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll @@ -59,12 +59,12 @@ ; GCN-LABEL: {{^}}reduced_nested_loop_conditions: -; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 1 -; GCN-NEXT: s_cbranch_scc1 +; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 +; GCN-NEXT: s_cbranch_scc0 ; FIXME: Should fold to unconditional branch? ; GCN: ; implicit-def -; GCN: s_cbranch_vccz +; GCN: s_cbranch_vccnz ; GCN: ds_read_b32 diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll index 1f915662ac0..7e7f6fc5e6d 100644 --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll @@ -89,11 +89,11 @@ declare float @llvm.fabs.f32(float) nounwind readnone ; This broke the old AMDIL cfg structurizer ; FUNC-LABEL: {{^}}loop_land_info_assert: -; SI: s_cmp_gt_i32 -; SI-NEXT: s_cbranch_scc0 [[ENDPGM:BB[0-9]+_[0-9]+]] +; SI: s_cmp_lt_i32 +; SI-NEXT: s_cbranch_scc1 [[ENDPGM:BB[0-9]+_[0-9]+]] -; SI: s_cmpk_gt_i32 -; SI-NEXT: s_cbranch_scc1 [[ENDPGM]] +; SI: s_cmpk_lt_i32 +; SI-NEXT: s_cbranch_scc0 [[ENDPGM]] ; SI: [[INFLOOP:BB[0-9]+_[0-9]+]] ; SI: s_cbranch_vccnz [[INFLOOP]] diff --git a/llvm/test/CodeGen/ARM/indirectbr.ll b/llvm/test/CodeGen/ARM/indirectbr.ll index a3ec2a7f3e7..db5014f9375 100644 --- a/llvm/test/CodeGen/ARM/indirectbr.ll +++ b/llvm/test/CodeGen/ARM/indirectbr.ll @@ -47,7 +47,7 @@ L3: ; preds = %L4, %bb2 br label %L2 L2: ; preds = %L3, %bb2 -; THUMB-LABEL: %L1.clone +; THUMB-LABEL: %.split4 ; THUMB: muls %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1] %phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1] diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll index 3bfc0de1b87..fd9121a59a4 100644 --- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll +++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll @@ -160,7 +160,7 @@ define signext i32 @zeroEqualityTest05() { ; Validate with memcmp()?: define signext i32 @equalityFoldTwoConstants() { ; CHECK-LABEL: equalityFoldTwoConstants: -; CHECK: # %bb.0: # %endblock +; CHECK: # %bb.0: # %loadbb ; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16) diff --git a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll index 83b1cd505db..c1e81074c86 100644 --- a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll +++ b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll @@ -7,7 +7,7 @@ define zeroext i1 @opeq1( ; PPC64LE-LABEL: opeq1: -; PPC64LE: # %bb.0: # %opeq1.exit +; PPC64LE: # %bb.0: # %entry ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: ld 4, 0(4) ; PPC64LE-NEXT: xor 3, 3, 4 diff --git a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll index 6886b4efa85..621bda04159 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll @@ -169,7 +169,7 @@ declare i32 @something(...) ; CHECK-NEXT: bne 0, .[[LOOP]] ; ; Next BB -; CHECK: %for.end +; CHECK: %for.exit ; CHECK: mtlr {{[0-9]+}} ; CHECK-NEXT: blr define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) { diff --git a/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll b/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll index 3988d9c8d5a..bf5754dc914 100644 --- a/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll +++ b/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll @@ -3,7 +3,7 @@ ; RUN: -ppc-convert-rr-to-ri -verify-machineinstrs | FileCheck %s define void @test(i32 zeroext %parts) { ; CHECK-LABEL: test: -; CHECK: # %bb.0: # %cond.end.i +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmplwi 0, 3, 1 ; CHECK-NEXT: bnelr+ 0 ; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa diff --git a/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll b/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll index d0afa3c8dfe..0372bd7beb4 100644 --- a/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll +++ b/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll @@ -25,7 +25,7 @@ bb3: br i1 undef, label %return, label %bb return: -; CHECK: %return +; CHECK: %bb3 ; 'mov sp, r7' would have left sp in an invalid state ; CHECK-NOT: mov sp, r7 ; CHECK-NOT: sub, sp, #4 diff --git a/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll b/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll index c71f37cee91..ba4638dfcb1 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll @@ -14,9 +14,6 @@ define i16 @main__getopt_internal_2E_exit_2E_ce(i32, i1 %b) nounwind { entry: br i1 %b, label %codeRepl127.exitStub, label %newFuncRoot -newFuncRoot: - br label %_getopt_internal.exit.ce - codeRepl127.exitStub: ; preds = %_getopt_internal.exit.ce ; Add an explicit edge back to before the jump table to ensure this block ; is placed first. @@ -103,6 +100,9 @@ codeRepl57.exitStub: ; preds = %_getopt_internal.exit.ce codeRepl103.exitStub: ; preds = %_getopt_internal.exit.ce ret i16 26 +newFuncRoot: + br label %_getopt_internal.exit.ce + _getopt_internal.exit.ce: ; preds = %newFuncRoot switch i32 %0, label %codeRepl127.exitStub [ i32 -1, label %parse_options.exit.loopexit.exitStub diff --git a/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll index 268d5af1571..4af4684d66b 100644 --- a/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll +++ b/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll @@ -6,9 +6,9 @@ define void @handle_vector_size_attribute() nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl 0, %eax ; CHECK-NEXT: decl %eax -; CHECK-NEXT: cmpl $2, %eax -; CHECK-NEXT: jae .LBB0_2 -; CHECK-NEXT: # %bb.1: # %cond_next129 +; CHECK-NEXT: cmpl $1, %eax +; CHECK-NEXT: ja .LBB0_2 +; CHECK-NEXT: # %bb.1: # %bb77 ; CHECK-NEXT: movb 0, %al ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: # kill: def $eax killed $eax def $ax diff --git a/llvm/test/CodeGen/X86/avx-cmp.ll b/llvm/test/CodeGen/X86/avx-cmp.ll index 2e151682a03..534a00050ad 100644 --- a/llvm/test/CodeGen/X86/avx-cmp.ll +++ b/llvm/test/CodeGen/X86/avx-cmp.ll @@ -26,12 +26,15 @@ declare void @scale() nounwind define void @render() nounwind { ; CHECK-LABEL: render: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: pushq %rax ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB2_6 ; CHECK-NEXT: # %bb.1: # %for.cond5.preheader ; CHECK-NEXT: xorl %ebx, %ebx +; CHECK-NEXT: movb $1, %bpl ; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB2_5: # %if.then @@ -43,8 +46,8 @@ define void @render() nounwind { ; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: # %bb.3: # %for.cond5 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je .LBB2_2 +; CHECK-NEXT: testb %bpl, %bpl +; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: # %bb.4: # %for.body33 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: vucomisd {{\.LCPI.*}}, %xmm0 @@ -52,7 +55,9 @@ define void @render() nounwind { ; CHECK-NEXT: jp .LBB2_5 ; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: .LBB2_6: # %for.end52 +; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx +; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq entry: br i1 undef, label %for.cond5, label %for.end52 diff --git a/llvm/test/CodeGen/X86/avx-splat.ll b/llvm/test/CodeGen/X86/avx-splat.ll index 4738262a97a..e1779ac8f18 100644 --- a/llvm/test/CodeGen/X86/avx-splat.ll +++ b/llvm/test/CodeGen/X86/avx-splat.ll @@ -58,7 +58,7 @@ entry: ; define <8 x float> @funcE() nounwind { ; CHECK-LABEL: funcE: -; CHECK: # %bb.0: # %for_exit499 +; CHECK: # %bb.0: # %allocas ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: # implicit-def: $ymm0 diff --git a/llvm/test/CodeGen/X86/avx2-vbroadcast.ll b/llvm/test/CodeGen/X86/avx2-vbroadcast.ll index 3ae6c0b9d81..5d7ac684e54 100644 --- a/llvm/test/CodeGen/X86/avx2-vbroadcast.ll +++ b/llvm/test/CodeGen/X86/avx2-vbroadcast.ll @@ -686,7 +686,7 @@ define void @crash() nounwind alwaysinline { ; X32-NEXT: ## %bb.2: ## %ret ; X32-NEXT: retl ; X32-NEXT: .p2align 4, 0x90 -; X32-NEXT: LBB33_1: ## %footer349VF +; X32-NEXT: LBB33_1: ## %footer329VF ; X32-NEXT: ## =>This Inner Loop Header: Depth=1 ; X32-NEXT: jmp LBB33_1 ; @@ -698,7 +698,7 @@ define void @crash() nounwind alwaysinline { ; X64-NEXT: ## %bb.2: ## %ret ; X64-NEXT: retq ; X64-NEXT: .p2align 4, 0x90 -; X64-NEXT: LBB33_1: ## %footer349VF +; X64-NEXT: LBB33_1: ## %footer329VF ; X64-NEXT: ## =>This Inner Loop Header: Depth=1 ; X64-NEXT: jmp LBB33_1 WGLoopsEntry: diff --git a/llvm/test/CodeGen/X86/avx512-i1test.ll b/llvm/test/CodeGen/X86/avx512-i1test.ll index df81b83d7c2..7cf86fe747f 100644 --- a/llvm/test/CodeGen/X86/avx512-i1test.ll +++ b/llvm/test/CodeGen/X86/avx512-i1test.ll @@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu" define void @func() { ; CHECK-LABEL: func: -; CHECK: # %bb.0: # %L_10 +; CHECK: # %bb.0: # %bb1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je .LBB0_1 @@ -70,7 +70,7 @@ define i64 @func2(i1 zeroext %i, i32 %j) { ; CHECK-NEXT: je .LBB1_1 ; CHECK-NEXT: # %bb.2: # %if.then ; CHECK-NEXT: jmp bar # TAILCALL -; CHECK-NEXT: .LBB1_1: # %return +; CHECK-NEXT: .LBB1_1: # %if.end ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: orq $-2, %rax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll index d97e367d8d0..a9d76cfde0d 100644 --- a/llvm/test/CodeGen/X86/block-placement.ll +++ b/llvm/test/CodeGen/X86/block-placement.ll @@ -317,7 +317,7 @@ define void @unnatural_cfg1() { ; a function. This is a gross CFG reduced out of the single source GCC. ; CHECK-LABEL: unnatural_cfg1 ; CHECK: %entry -; CHECK: %loop.body1 +; CHECK: %loop.header ; CHECK: %loop.body2 ; CHECK: %loop.body3 @@ -611,7 +611,7 @@ define void @test_unnatural_cfg_backwards_inner_loop() { ; CHECK-LABEL: test_unnatural_cfg_backwards_inner_loop ; CHECK: %entry ; CHECK: %loop2b -; CHECK: %loop1 +; CHECK: %loop3 entry: br i1 undef, label %loop2a, label %body diff --git a/llvm/test/CodeGen/X86/hoist-spill.ll b/llvm/test/CodeGen/X86/hoist-spill.ll index 03f558fc3ae..6a3f5ca01e8 100644 --- a/llvm/test/CodeGen/X86/hoist-spill.ll +++ b/llvm/test/CodeGen/X86/hoist-spill.ll @@ -48,9 +48,6 @@ for.cond: ; preds = %for.inc14, %entry %cmp326 = icmp sgt i32 %k.0, %p1 br i1 %cmp326, label %for.cond4.preheader, label %for.body.preheader -for.body.preheader: ; preds = %for.cond - br label %for.body - for.cond4.preheader: ; preds = %for.body, %for.cond %k.1.lcssa = phi i32 [ %k.0, %for.cond ], [ %add, %for.body ] %cmp528 = icmp sgt i32 %sub., %p1 @@ -95,6 +92,9 @@ vector.body: ; preds = %vector.body, %vecto middle.block: ; preds = %vector.body, %vector.body.preheader.split br i1 undef, label %for.inc14, label %for.body6 +for.body.preheader: ; preds = %for.cond + br label %for.body + for.body: ; preds = %for.body, %for.body.preheader %k.127 = phi i32 [ %k.0, %for.body.preheader ], [ %add, %for.body ] %add = add nsw i32 %k.127, 1 diff --git a/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll index 3112e1ab4be..98af189f86d 100644 --- a/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll +++ b/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll @@ -3,7 +3,7 @@ define fastcc i32 @t() nounwind { ; CHECK-LABEL: t: -; CHECK: # %bb.0: # %walkExprTree.exit +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movzwl 0, %eax ; CHECK-NEXT: orl $2, %eax ; CHECK-NEXT: movw %ax, 0 diff --git a/llvm/test/CodeGen/X86/memcmp-mergeexpand.ll b/llvm/test/CodeGen/X86/memcmp-mergeexpand.ll index 1c470177c27..785ba403465 100644 --- a/llvm/test/CodeGen/X86/memcmp-mergeexpand.ll +++ b/llvm/test/CodeGen/X86/memcmp-mergeexpand.ll @@ -8,7 +8,7 @@ define zeroext i1 @opeq1( ; X86-LABEL: opeq1: -; X86: # %bb.0: # %opeq1.exit +; X86: # %bb.0: # %entry ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl (%ecx), %edx @@ -20,7 +20,7 @@ define zeroext i1 @opeq1( ; X86-NEXT: retl ; ; X64-LABEL: opeq1: -; X64: # %bb.0: # %opeq1.exit +; X64: # %bb.0: # %entry ; X64-NEXT: movq (%rdi), %rax ; X64-NEXT: cmpq (%rsi), %rax ; X64-NEXT: sete %al diff --git a/llvm/test/CodeGen/X86/pr32108.ll b/llvm/test/CodeGen/X86/pr32108.ll index ff1b7d3401f..bde5daff285 100644 --- a/llvm/test/CodeGen/X86/pr32108.ll +++ b/llvm/test/CodeGen/X86/pr32108.ll @@ -3,7 +3,7 @@ define void @pr32108() { ; CHECK-LABEL: pr32108: -; CHECK: # %bb.0: # %CF257 +; CHECK: # %bb.0: # %BB ; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_1: # %CF244 diff --git a/llvm/test/CodeGen/X86/setcc-lowering.ll b/llvm/test/CodeGen/X86/setcc-lowering.ll index 11e453e1550..ce057b28cc9 100644 --- a/llvm/test/CodeGen/X86/setcc-lowering.ll +++ b/llvm/test/CodeGen/X86/setcc-lowering.ll @@ -43,7 +43,7 @@ entry: define void @pr26232(i64 %a, <16 x i1> %b) { ; AVX-LABEL: pr26232: -; AVX: # %bb.0: # %for_loop599.preheader +; AVX: # %bb.0: # %allocas ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; AVX-NEXT: .p2align 4, 0x90 @@ -64,7 +64,7 @@ define void @pr26232(i64 %a, <16 x i1> %b) { ; AVX-NEXT: retq ; ; KNL-32-LABEL: pr26232: -; KNL-32: # %bb.0: # %for_loop599.preheader +; KNL-32: # %bb.0: # %allocas ; KNL-32-NEXT: pushl %esi ; KNL-32-NEXT: .cfi_def_cfa_offset 8 ; KNL-32-NEXT: .cfi_offset %esi, -8 diff --git a/llvm/test/CodeGen/X86/split-store.ll b/llvm/test/CodeGen/X86/split-store.ll index 64238901d10..575f46c04c0 100644 --- a/llvm/test/CodeGen/X86/split-store.ll +++ b/llvm/test/CodeGen/X86/split-store.ll @@ -232,7 +232,7 @@ define void @int1_int1_pair(i1 signext %tmp1, i1 signext %tmp2, i2* %ref.tmp) { define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) { ; CHECK-LABEL: mbb_int32_float_pair: -; CHECK: # %bb.0: # %next +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl %edi, (%rsi) ; CHECK-NEXT: movss %xmm0, 4(%rsi) ; CHECK-NEXT: retq @@ -250,7 +250,7 @@ next: define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, i64* %ref.tmp, i64* %ref.tmp1, i1 %cmp) { ; CHECK-LABEL: mbb_int32_float_multi_stores: -; CHECK: # %bb.0: # %bb1 +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl %edi, (%rsi) ; CHECK-NEXT: movss %xmm0, 4(%rsi) ; CHECK-NEXT: testb $1, %cl diff --git a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll index 736a6d8500d..2f9cc474d27 100644 --- a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll +++ b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll @@ -10,7 +10,7 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK-NOT: # %{{[a-zA-Z_]+}} ; CHECK: # %inner_loop_latch ; CHECK-NOT: # %{{[a-zA-Z_]+}} -; CHECK: # %inner_loop_test +; CHECK: # %inner_loop_top ; CHECK-NOT: # %{{[a-zA-Z_]+}} ; CHECK: # %exit define void @tail_dup_merge_loops(i32 %a, i8* %b, i8* %c) local_unnamed_addr #0 { |
