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-rw-r--r--llvm/test/CodeGen/SystemZ/locr-legal-regclass.ll20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/locr-legal-regclass.ll b/llvm/test/CodeGen/SystemZ/locr-legal-regclass.ll
new file mode 100644
index 00000000000..1f792439a49
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/locr-legal-regclass.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs | FileCheck %s
+;
+; Test that early if conversion produces LOCR with operands of the right
+; register classes.
+
+define void @autogen_SD4739(i8*) {
+; CHECK-NOT: Expected a GR32Bit register, but got a GRX32Bit register
+BB:
+ %L34 = load i8, i8* %0
+ %Cmp56 = icmp sgt i8 undef, %L34
+ br label %CF246
+
+CF246: ; preds = %CF246, %BB
+ %Sl163 = select i1 %Cmp56, i8 %L34, i8 undef
+ br i1 undef, label %CF246, label %CF248
+
+CF248: ; preds = %CF248, %CF246
+ store i8 %Sl163, i8* %0
+ br label %CF248
+}
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