summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/Mips/fcmp.ll140
-rw-r--r--llvm/test/CodeGen/Mips/selectcc.ll2
2 files changed, 85 insertions, 57 deletions
diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index 052ab0d13ec..e22b12a5d53 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -55,9 +55,10 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
@@ -88,9 +89,10 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
@@ -121,9 +123,10 @@ define i32 @oge_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
@@ -154,9 +157,10 @@ define i32 @olt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
@@ -187,9 +191,10 @@ define i32 @ole_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
@@ -222,9 +227,10 @@ define i32 @one_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
@@ -258,9 +264,10 @@ define i32 @ord_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
@@ -292,9 +299,10 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
@@ -325,9 +333,10 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
@@ -358,9 +367,10 @@ define i32 @uge_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
@@ -391,9 +401,10 @@ define i32 @ult_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
@@ -424,9 +435,10 @@ define i32 @ule_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
@@ -459,9 +471,10 @@ define i32 @une_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
@@ -493,9 +506,10 @@ define i32 @uno_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
@@ -560,9 +574,10 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
@@ -593,9 +608,10 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
@@ -626,9 +642,10 @@ define i32 @oge_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
@@ -659,9 +676,10 @@ define i32 @olt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
@@ -692,9 +710,10 @@ define i32 @ole_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
@@ -727,9 +746,10 @@ define i32 @one_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
@@ -763,9 +783,10 @@ define i32 @ord_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
@@ -797,9 +818,10 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
@@ -830,9 +852,10 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
@@ -863,9 +886,10 @@ define i32 @uge_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
@@ -896,9 +920,10 @@ define i32 @ult_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
@@ -929,9 +954,10 @@ define i32 @ule_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
@@ -964,9 +990,10 @@ define i32 @une_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14
-; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
@@ -998,9 +1025,10 @@ define i32 @uno_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14
-; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
diff --git a/llvm/test/CodeGen/Mips/selectcc.ll b/llvm/test/CodeGen/Mips/selectcc.ll
index 90e52bd9db3..865e4b38aca 100644
--- a/llvm/test/CodeGen/Mips/selectcc.ll
+++ b/llvm/test/CodeGen/Mips/selectcc.ll
@@ -18,10 +18,10 @@ entry:
; SOURCE-SCHED: lw
; SOURCE-SCHED: lui
; SOURCE-SCHED: sw
-; SOURCE-SCHED: c.olt.s
; SOURCE-SCHED: lw
; SOURCE-SCHED: lwc1
; SOURCE-SCHED: mtc1
+; SOURCE-SCHED: c.olt.s
; SOURCE-SCHED: jr
store float 0.000000e+00, float* @gf0, align 4
store float 1.000000e+00, float* @gf1, align 4
OpenPOWER on IntegriCloud