diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll | 36 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll | 34 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll | 6 |
4 files changed, 45 insertions, 45 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll index 36aa6779d38..98a3f170323 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_default_ci: -; GCN: compute_pgm_rsrc1_float_mode = 192 -; GCN: compute_pgm_rsrc1_dx10_clamp = 1 -; GCN: compute_pgm_rsrc1_ieee_mode = 0 +; GCN: float_mode = 192 +; GCN: enable_dx10_clamp = 1 +; GCN: enable_ieee_mode = 0 define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 @@ -11,9 +11,9 @@ define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %ou } ; GCN-LABEL: {{^}}test_default_vi: -; GCN: compute_pgm_rsrc1_float_mode = 192 -; GCN: compute_pgm_rsrc1_dx10_clamp = 1 -; GCN: compute_pgm_rsrc1_ieee_mode = 0 +; GCN: float_mode = 192 +; GCN: enable_dx10_clamp = 1 +; GCN: enable_ieee_mode = 0 define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 @@ -21,9 +21,9 @@ define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %ou } ; GCN-LABEL: {{^}}test_f64_denormals: -; GCN: compute_pgm_rsrc1_float_mode = 192 -; GCN: compute_pgm_rsrc1_dx10_clamp = 1 -; GCN: compute_pgm_rsrc1_ieee_mode = 0 +; GCN: float_mode = 192 +; GCN: enable_dx10_clamp = 1 +; GCN: enable_ieee_mode = 0 define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 @@ -31,9 +31,9 @@ define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* } ; GCN-LABEL: {{^}}test_f32_denormals: -; GCN: compute_pgm_rsrc1_float_mode = 48 -; GCN: compute_pgm_rsrc1_dx10_clamp = 1 -; GCN: compute_pgm_rsrc1_ieee_mode = 0 +; GCN: float_mode = 48 +; GCN: enable_dx10_clamp = 1 +; GCN: enable_ieee_mode = 0 define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 @@ -41,9 +41,9 @@ define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* } ; GCN-LABEL: {{^}}test_f32_f64_denormals: -; GCN: compute_pgm_rsrc1_float_mode = 240 -; GCN: compute_pgm_rsrc1_dx10_clamp = 1 -; GCN: compute_pgm_rsrc1_ieee_mode = 0 +; GCN: float_mode = 240 +; GCN: enable_dx10_clamp = 1 +; GCN: enable_ieee_mode = 0 define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 @@ -51,9 +51,9 @@ define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace( } ; GCN-LABEL: {{^}}test_no_denormals: -; GCN: compute_pgm_rsrc1_float_mode = 0 -; GCN: compute_pgm_rsrc1_dx10_clamp = 1 -; GCN: compute_pgm_rsrc1_ieee_mode = 0 +; GCN: float_mode = 0 +; GCN: enable_dx10_clamp = 1 +; GCN: enable_ieee_mode = 0 define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll index 099f0639b34..4f6dbf9dc2b 100644 --- a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll +++ b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll @@ -18,13 +18,13 @@ ; GCNHSA: .amd_kernel_code_t -; GCNHSA: compute_pgm_rsrc2_scratch_en = 1 -; GCNHSA: compute_pgm_rsrc2_user_sgpr = 8 -; GCNHSA: compute_pgm_rsrc2_tgid_x_en = 1 -; GCNHSA: compute_pgm_rsrc2_tgid_y_en = 0 -; GCNHSA: compute_pgm_rsrc2_tgid_z_en = 0 -; GCNHSA: compute_pgm_rsrc2_tg_size_en = 0 -; GCNHSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 +; GCNHSA: enable_sgpr_private_segment_wave_byte_offset = 1 +; GCNHSA: user_sgpr_count = 8 +; GCNHSA: enable_sgpr_workgroup_id_x = 1 +; GCNHSA: enable_sgpr_workgroup_id_y = 0 +; GCNHSA: enable_sgpr_workgroup_id_z = 0 +; GCNHSA: enable_sgpr_workgroup_info = 0 +; GCNHSA: enable_vgpr_workitem_id = 0 ; GCNHSA: enable_sgpr_private_segment_buffer = 1 ; GCNHSA: enable_sgpr_dispatch_ptr = 0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll index c22eac7e271..75a9ec91eca 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll @@ -10,12 +10,12 @@ declare i32 @llvm.amdgcn.workgroup.id.z() #0 ; ALL-LABEL {{^}}test_workgroup_id_x: ; HSA: .amd_kernel_code_t -; HSA: compute_pgm_rsrc2_user_sgpr = 6 -; HSA: compute_pgm_rsrc2_tgid_x_en = 1 -; HSA: compute_pgm_rsrc2_tgid_y_en = 0 -; HSA: compute_pgm_rsrc2_tgid_z_en = 0 -; HSA: compute_pgm_rsrc2_tg_size_en = 0 -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 +; HSA: user_sgpr_count = 6 +; HSA: enable_sgpr_workgroup_id_x = 1 +; HSA: enable_sgpr_workgroup_id_y = 0 +; HSA: enable_sgpr_workgroup_id_z = 0 +; HSA: enable_sgpr_workgroup_info = 0 +; HSA: enable_vgpr_workitem_id = 0 ; HSA: enable_sgpr_grid_workgroup_count_x = 0 ; HSA: enable_sgpr_grid_workgroup_count_y = 0 ; HSA: enable_sgpr_grid_workgroup_count_z = 0 @@ -40,11 +40,11 @@ define void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 { } ; ALL-LABEL {{^}}test_workgroup_id_y: -; HSA: compute_pgm_rsrc2_user_sgpr = 6 -; HSA: compute_pgm_rsrc2_tgid_x_en = 1 -; HSA: compute_pgm_rsrc2_tgid_y_en = 1 -; HSA: compute_pgm_rsrc2_tgid_z_en = 0 -; HSA: compute_pgm_rsrc2_tg_size_en = 0 +; HSA: user_sgpr_count = 6 +; HSA: enable_sgpr_workgroup_id_x = 1 +; HSA: enable_sgpr_workgroup_id_y = 1 +; HSA: enable_sgpr_workgroup_id_z = 0 +; HSA: enable_sgpr_workgroup_info = 0 ; HSA: enable_sgpr_grid_workgroup_count_x = 0 ; HSA: enable_sgpr_grid_workgroup_count_y = 0 ; HSA: enable_sgpr_grid_workgroup_count_z = 0 @@ -68,12 +68,12 @@ define void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 { } ; ALL-LABEL {{^}}test_workgroup_id_z: -; HSA: compute_pgm_rsrc2_user_sgpr = 6 -; HSA: compute_pgm_rsrc2_tgid_x_en = 1 -; HSA: compute_pgm_rsrc2_tgid_y_en = 0 -; HSA: compute_pgm_rsrc2_tgid_z_en = 1 -; HSA: compute_pgm_rsrc2_tg_size_en = 0 -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 +; HSA: user_sgpr_count = 6 +; HSA: enable_sgpr_workgroup_id_x = 1 +; HSA: enable_sgpr_workgroup_id_y = 0 +; HSA: enable_sgpr_workgroup_id_z = 1 +; HSA: enable_sgpr_workgroup_info = 0 +; HSA: enable_vgpr_workitem_id = 0 ; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll index 28ef7b82ef8..393a593fad0 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll @@ -12,7 +12,7 @@ declare i32 @llvm.amdgcn.workitem.id.z() #0 ; MESA-NEXT: .long 132{{$}} ; ALL-LABEL {{^}}test_workitem_id_x: -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 +; HSA: enable_vgpr_workitem_id = 0 ; ALL-NOT: v0 ; ALL: {{buffer|flat}}_store_dword {{.*}}v0 @@ -27,7 +27,7 @@ define void @test_workitem_id_x(i32 addrspace(1)* %out) #1 { ; MESA-NEXT: .long 2180{{$}} ; ALL-LABEL {{^}}test_workitem_id_y: -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1 +; HSA: enable_vgpr_workitem_id = 1 ; ALL-NOT: v1 ; ALL: {{buffer|flat}}_store_dword {{.*}}v1 @@ -42,7 +42,7 @@ define void @test_workitem_id_y(i32 addrspace(1)* %out) #1 { ; MESA-NEXT: .long 4228{{$}} ; ALL-LABEL {{^}}test_workitem_id_z: -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2 +; HSA: enable_vgpr_workitem_id = 2 ; ALL-NOT: v2 ; ALL: {{buffer|flat}}_store_dword {{.*}}v2 |
