diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/br-cond-not-merge.ll | 32 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/cmov.ll | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/dagcombine-and-setcc.ll | 7 |
3 files changed, 39 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/br-cond-not-merge.ll b/llvm/test/CodeGen/AArch64/br-cond-not-merge.ll new file mode 100644 index 00000000000..be8797176e6 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/br-cond-not-merge.ll @@ -0,0 +1,32 @@ +; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s + +declare void @foo() + +; Check that the inverted or doesn't inhibit the splitting of the +; complex conditional into three branch instructions. +; CHECK-LABEL: test_and_not +; CHECK: cbz w0, [[L:\.LBB[0-9_]+]] +; CHECK: cmp w1, #2 +; CHECK: b.lo [[L]] +; CHECK: cmp w2, #2 +; CHECK: b.hi [[L]] +define void @test_and_not(i32 %a, i32 %b, i32 %c) { +bb1: + %cmp1 = icmp ult i32 %a, 1 + %cmp2 = icmp ult i32 %b, 2 + %cmp3 = icmp ult i32 %c, 3 + %or = or i1 %cmp1, %cmp2 + %not.or = xor i1 %or, -1 + %and = and i1 %not.or, %cmp3 + br i1 %and, label %bb2, label %bb3 + +bb2: + ret void + +bb3: + call void @foo() + ret void +} + + + diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll index 0060539c691..d901f16e5c7 100644 --- a/llvm/test/CodeGen/X86/cmov.ll +++ b/llvm/test/CodeGen/X86/cmov.ll @@ -70,7 +70,7 @@ define void @test3(i64 %a, i64 %b, i1 %p) nounwind { @g_100 = external global i8 ; <i8*> [#uses=2] @_2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1] -define i32 @test4() nounwind { +define i1 @test4() nounwind { entry: %0 = load i8, i8* @g_3, align 1 ; <i8> [#uses=2] %1 = sext i8 %0 to i32 ; <i32> [#uses=1] @@ -107,10 +107,11 @@ bb.i.i: ; preds = %func_4.exit.i func_1.exit: ; preds = %bb.i.i, %func_4.exit.i %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2] + %ret = phi i1 [ 0, %bb.i.i ], [ %.not.i, %func_4.exit.i ] store i8 %g_96.tmp.0.i, i8* @g_96 %6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1] %7 = tail call i32 (i8*, ...) @printf(i8* noalias getelementptr ([15 x i8], [15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0] - ret i32 0 + ret i1 %ret } declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/llvm/test/CodeGen/X86/dagcombine-and-setcc.ll b/llvm/test/CodeGen/X86/dagcombine-and-setcc.ll index 57adc8bc5da..f7302aee65c 100644 --- a/llvm/test/CodeGen/X86/dagcombine-and-setcc.ll +++ b/llvm/test/CodeGen/X86/dagcombine-and-setcc.ll @@ -12,10 +12,11 @@ declare i32 @printf(i8* nocapture readonly, ...) ;CHECK: cmpl -;CHECK: setg +;CHECK: setl ;CHECK: cmpl -;CHECK: setg -;CHECK: andb +;CHECK: setl +;CHECK: orb +;CHECK: je @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 ; Function Attrs: optsize ssp uwtable |
