diff options
Diffstat (limited to 'llvm/test/CodeGen')
5 files changed, 607 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir new file mode 100644 index 00000000000..f62ad974264 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir @@ -0,0 +1,114 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=i686-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- | + ; ModuleID = 'sdiv.ll' + source_filename = "sdiv.ll" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + + define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { + %res = sdiv i8 %arg1, %arg2 + ret i8 %res + } + + define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { + %res = sdiv i16 %arg1, %arg2 + ret i16 %res + } + + define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { + %res = sdiv i32 %arg1, %arg2 + ret i32 %res + } + +... +--- +name: test_sdiv_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i8 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: $al = COPY [[SDIV]](s8) + ; CHECK: RET 0, implicit $al + %2:_(s32) = COPY $edi + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $esi + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_SDIV %0, %1 + $al = COPY %4(s8) + RET 0, implicit $al + +... +--- +name: test_sdiv_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i16 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: $ax = COPY [[SDIV]](s16) + ; CHECK: RET 0, implicit $ax + %2:_(s32) = COPY $edi + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $esi + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_SDIV %0, %1 + $ax = COPY %4(s16) + RET 0, implicit $ax + +... +--- +name: test_sdiv_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i32 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK: $eax = COPY [[SDIV]](s32) + ; CHECK: RET 0, implicit $eax + %0:_(s32) = COPY $edi + %1:_(s32) = COPY $esi + %2:_(s32) = G_SDIV %0, %1 + $eax = COPY %2(s32) + RET 0, implicit $eax + +... diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir new file mode 100644 index 00000000000..ffe1db0aa3f --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir @@ -0,0 +1,128 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- | + ; ModuleID = 'sdiv.ll' + source_filename = "sdiv.ll" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + + define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { + %res = sdiv i8 %arg1, %arg2 + ret i8 %res + } + + define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { + %res = sdiv i16 %arg1, %arg2 + ret i16 %res + } + + define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { + %res = sdiv i32 %arg1, %arg2 + ret i32 %res + } + +... +--- +name: test_sdiv_i8 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i8 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; CHECK: [[COPY2:%[0-9]+]]:gr32_abcd = COPY $esi + ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit + ; CHECK: $ax = MOVSX16rr8 [[COPY1]] + ; CHECK: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax + ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $al + ; CHECK: $al = COPY [[COPY4]] + ; CHECK: RET 0, implicit $al + %2:gpr(s32) = COPY $edi + %0:gpr(s8) = G_TRUNC %2(s32) + %3:gpr(s32) = COPY $esi + %1:gpr(s8) = G_TRUNC %3(s32) + %4:gpr(s8) = G_SDIV %0, %1 + $al = COPY %4(s8) + RET 0, implicit $al + +... +--- +name: test_sdiv_i16 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i16 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi + ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit + ; CHECK: $ax = COPY [[COPY1]] + ; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax + ; CHECK: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx + ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $ax + ; CHECK: $ax = COPY [[COPY4]] + ; CHECK: RET 0, implicit $ax + %2:gpr(s32) = COPY $edi + %0:gpr(s16) = G_TRUNC %2(s32) + %3:gpr(s32) = COPY $esi + %1:gpr(s16) = G_TRUNC %3(s32) + %4:gpr(s16) = G_SDIV %0, %1 + $ax = COPY %4(s16) + RET 0, implicit $ax + +... +--- +name: test_sdiv_i32 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i32 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK: $eax = COPY [[COPY]] + ; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax + ; CHECK: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx + ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $eax + ; CHECK: $eax = COPY [[COPY2]] + ; CHECK: RET 0, implicit $eax + %0:gpr(s32) = COPY $edi + %1:gpr(s32) = COPY $esi + %2:gpr(s32) = G_SDIV %0, %1 + $eax = COPY %2(s32) + RET 0, implicit $eax + +... diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll index 327992b6eba..907a8fd38cb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll @@ -129,3 +129,59 @@ define i64 @zext_i32_to_i64(i32 %val) { %res = zext i32 %val to i64 ret i64 %res } + +define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { + ; CHECK-LABEL: name: test_sdiv_i8 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: $al = COPY [[SDIV]](s8) + ; CHECK: RET 0, implicit $al + %res = sdiv i8 %arg1, %arg2 + ret i8 %res +} + +define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { + ; CHECK-LABEL: name: test_sdiv_i16 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: $ax = COPY [[SDIV]](s16) + ; CHECK: RET 0, implicit $ax + %res = sdiv i16 %arg1, %arg2 + ret i16 %res +} + +define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { + ; CHECK-LABEL: name: test_sdiv_i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK: $eax = COPY [[SDIV]](s32) + ; CHECK: RET 0, implicit $eax + %res = sdiv i32 %arg1, %arg2 + ret i32 %res +} + +define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) { + ; CHECK-LABEL: name: test_sdiv_i64 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $rdi, $rsi + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi + ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK: $rax = COPY [[SDIV]](s64) + ; CHECK: RET 0, implicit $rax + %res = sdiv i64 %arg1, %arg2 + ret i64 %res +} diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir new file mode 100644 index 00000000000..41ae1dc07d9 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir @@ -0,0 +1,145 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- | + ; ModuleID = 'sdiv.ll' + source_filename = "sdiv.ll" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + + define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { + %res = sdiv i8 %arg1, %arg2 + ret i8 %res + } + + define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { + %res = sdiv i16 %arg1, %arg2 + ret i16 %res + } + + define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { + %res = sdiv i32 %arg1, %arg2 + ret i32 %res + } + + define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) { + %res = sdiv i64 %arg1, %arg2 + ret i64 %res + } + +... +--- +name: test_sdiv_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i8 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: $al = COPY [[SDIV]](s8) + ; CHECK: RET 0, implicit $al + %2:_(s32) = COPY $edi + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $esi + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_SDIV %0, %1 + $al = COPY %4(s8) + RET 0, implicit $al + +... +--- +name: test_sdiv_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i16 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: $ax = COPY [[SDIV]](s16) + ; CHECK: RET 0, implicit $ax + %2:_(s32) = COPY $edi + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $esi + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_SDIV %0, %1 + $ax = COPY %4(s16) + RET 0, implicit $ax + +... +--- +name: test_sdiv_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i32 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi + ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK: $eax = COPY [[SDIV]](s32) + ; CHECK: RET 0, implicit $eax + %0:_(s32) = COPY $edi + %1:_(s32) = COPY $esi + %2:_(s32) = G_SDIV %0, %1 + $eax = COPY %2(s32) + RET 0, implicit $eax + +... +--- +name: test_sdiv_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $rdi, $rsi + + ; CHECK-LABEL: name: test_sdiv_i64 + ; CHECK: liveins: $rdi, $rsi + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi + ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK: $rax = COPY [[SDIV]](s64) + ; CHECK: RET 0, implicit $rax + %0:_(s64) = COPY $rdi + %1:_(s64) = COPY $rsi + %2:_(s64) = G_SDIV %0, %1 + $rax = COPY %2(s64) + RET 0, implicit $rax + +... diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir new file mode 100644 index 00000000000..7dffbd86b21 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir @@ -0,0 +1,164 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- | + ; ModuleID = 'sdiv.ll' + source_filename = "sdiv.ll" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + + define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { + %res = sdiv i8 %arg1, %arg2 + ret i8 %res + } + + define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { + %res = sdiv i16 %arg1, %arg2 + ret i16 %res + } + + define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { + %res = sdiv i32 %arg1, %arg2 + ret i32 %res + } + + define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) { + %res = sdiv i64 %arg1, %arg2 + ret i64 %res + } + +... +--- +name: test_sdiv_i8 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i8 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi + ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit + ; CHECK: $ax = MOVSX16rr8 [[COPY1]] + ; CHECK: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax + ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $al + ; CHECK: $al = COPY [[COPY4]] + ; CHECK: RET 0, implicit $al + %2:gpr(s32) = COPY $edi + %0:gpr(s8) = G_TRUNC %2(s32) + %3:gpr(s32) = COPY $esi + %1:gpr(s8) = G_TRUNC %3(s32) + %4:gpr(s8) = G_SDIV %0, %1 + $al = COPY %4(s8) + RET 0, implicit $al + +... +--- +name: test_sdiv_i16 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i16 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi + ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit + ; CHECK: $ax = COPY [[COPY1]] + ; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax + ; CHECK: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx + ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $ax + ; CHECK: $ax = COPY [[COPY4]] + ; CHECK: RET 0, implicit $ax + %2:gpr(s32) = COPY $edi + %0:gpr(s16) = G_TRUNC %2(s32) + %3:gpr(s32) = COPY $esi + %1:gpr(s16) = G_TRUNC %3(s32) + %4:gpr(s16) = G_SDIV %0, %1 + $ax = COPY %4(s16) + RET 0, implicit $ax + +... +--- +name: test_sdiv_i32 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $edi, $esi + + ; CHECK-LABEL: name: test_sdiv_i32 + ; CHECK: liveins: $edi, $esi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK: $eax = COPY [[COPY]] + ; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax + ; CHECK: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx + ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $eax + ; CHECK: $eax = COPY [[COPY2]] + ; CHECK: RET 0, implicit $eax + %0:gpr(s32) = COPY $edi + %1:gpr(s32) = COPY $esi + %2:gpr(s32) = G_SDIV %0, %1 + $eax = COPY %2(s32) + RET 0, implicit $eax + +... +--- +name: test_sdiv_i64 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +body: | + bb.1 (%ir-block.0): + liveins: $rdi, $rsi + + ; CHECK-LABEL: name: test_sdiv_i64 + ; CHECK: liveins: $rdi, $rsi + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi + ; CHECK: $rax = COPY [[COPY]] + ; CHECK: CQO implicit-def $rax, implicit-def $rdx, implicit $rax + ; CHECK: IDIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx + ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rax + ; CHECK: $rax = COPY [[COPY2]] + ; CHECK: RET 0, implicit $rax + %0:gpr(s64) = COPY $rdi + %1:gpr(s64) = COPY $rsi + %2:gpr(s64) = G_SDIV %0, %1 + $rax = COPY %2(s64) + RET 0, implicit $rax + +... |
