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-rw-r--r--llvm/test/CodeGen/AArch64/fast-isel-logic-op.ll176
1 files changed, 176 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-logic-op.ll b/llvm/test/CodeGen/AArch64/fast-isel-logic-op.ll
index 1efe4505f9e..152fff808ad 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-logic-op.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-logic-op.ll
@@ -2,6 +2,29 @@
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
; AND
+define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {
+; CHECK-LABEL: and_rr_i1
+; CHECK: and [[REG:w[0-9]+]], w0, w1
+ %1 = and i1 %a, %b
+ ret i1 %1
+}
+
+define zeroext i8 @and_rr_i8(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: and_rr_i8
+; CHECK: and [[REG:w[0-9]+]], w0, w1
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
+ %1 = and i8 %a, %b
+ ret i8 %1
+}
+
+define zeroext i16 @and_rr_i16(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: and_rr_i16
+; CHECK: and [[REG:w[0-9]+]], w0, w1
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
+ %1 = and i16 %a, %b
+ ret i16 %1
+}
+
define i32 @and_rr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: and_rr_i32
; CHECK: and w0, w0, w1
@@ -16,6 +39,27 @@ define i64 @and_rr_i64(i64 %a, i64 %b) {
ret i64 %1
}
+define zeroext i1 @and_ri_i1(i1 signext %a) {
+; CHECK-LABEL: and_ri_i1
+; CHECK: and {{w[0-9]+}}, w0, #0x1
+ %1 = and i1 %a, 1
+ ret i1 %1
+}
+
+define zeroext i8 @and_ri_i8(i8 signext %a) {
+; CHECK-LABEL: and_ri_i8
+; CHECK: and {{w[0-9]+}}, w0, #0xf
+ %1 = and i8 %a, 15
+ ret i8 %1
+}
+
+define zeroext i16 @and_ri_i16(i16 signext %a) {
+; CHECK-LABEL: and_ri_i16
+; CHECK: and {{w[0-9]+}}, w0, #0xff
+ %1 = and i16 %a, 255
+ ret i16 %1
+}
+
define i32 @and_ri_i32(i32 %a) {
; CHECK-LABEL: and_ri_i32
; CHECK: and w0, w0, #0xff
@@ -30,6 +74,24 @@ define i64 @and_ri_i64(i64 %a) {
ret i64 %1
}
+define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: and_rs_i8
+; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #4
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
+ %1 = shl i8 %b, 4
+ %2 = and i8 %a, %1
+ ret i8 %2
+}
+
+define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: and_rs_i16
+; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #8
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
+ %1 = shl i16 %b, 8
+ %2 = and i16 %a, %1
+ ret i16 %2
+}
+
define i32 @and_rs_i32(i32 %a, i32 %b) {
; CHECK-LABEL: and_rs_i32
; CHECK: and w0, w0, w1, lsl #8
@@ -47,6 +109,29 @@ define i64 @and_rs_i64(i64 %a, i64 %b) {
}
; OR
+define zeroext i1 @or_rr_i1(i1 signext %a, i1 signext %b) {
+; CHECK-LABEL: or_rr_i1
+; CHECK: orr [[REG:w[0-9]+]], w0, w1
+ %1 = or i1 %a, %b
+ ret i1 %1
+}
+
+define zeroext i8 @or_rr_i8(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: or_rr_i8
+; CHECK: orr [[REG:w[0-9]+]], w0, w1
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
+ %1 = or i8 %a, %b
+ ret i8 %1
+}
+
+define zeroext i16 @or_rr_i16(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: or_rr_i16
+; CHECK: orr [[REG:w[0-9]+]], w0, w1
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
+ %1 = or i16 %a, %b
+ ret i16 %1
+}
+
define i32 @or_rr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: or_rr_i32
; CHECK: orr w0, w0, w1
@@ -61,6 +146,22 @@ define i64 @or_rr_i64(i64 %a, i64 %b) {
ret i64 %1
}
+define zeroext i8 @or_ri_i8(i8 %a) {
+; CHECK-LABEL: or_ri_i8
+; CHECK: orr [[REG:w[0-9]+]], w0, #0xf
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
+ %1 = or i8 %a, 15
+ ret i8 %1
+}
+
+define zeroext i16 @or_ri_i16(i16 %a) {
+; CHECK-LABEL: or_ri_i16
+; CHECK: orr [[REG:w[0-9]+]], w0, #0xff
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
+ %1 = or i16 %a, 255
+ ret i16 %1
+}
+
define i32 @or_ri_i32(i32 %a) {
; CHECK-LABEL: or_ri_i32
; CHECK: orr w0, w0, #0xff
@@ -75,6 +176,24 @@ define i64 @or_ri_i64(i64 %a) {
ret i64 %1
}
+define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: or_rs_i8
+; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #4
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
+ %1 = shl i8 %b, 4
+ %2 = or i8 %a, %1
+ ret i8 %2
+}
+
+define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: or_rs_i16
+; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #8
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
+ %1 = shl i16 %b, 8
+ %2 = or i16 %a, %1
+ ret i16 %2
+}
+
define i32 @or_rs_i32(i32 %a, i32 %b) {
; CHECK-LABEL: or_rs_i32
; CHECK: orr w0, w0, w1, lsl #8
@@ -92,6 +211,29 @@ define i64 @or_rs_i64(i64 %a, i64 %b) {
}
; XOR
+define zeroext i1 @xor_rr_i1(i1 signext %a, i1 signext %b) {
+; CHECK-LABEL: xor_rr_i1
+; CHECK: eor [[REG:w[0-9]+]], w0, w1
+ %1 = xor i1 %a, %b
+ ret i1 %1
+}
+
+define zeroext i8 @xor_rr_i8(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: xor_rr_i8
+; CHECK: eor [[REG:w[0-9]+]], w0, w1
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
+ %1 = xor i8 %a, %b
+ ret i8 %1
+}
+
+define zeroext i16 @xor_rr_i16(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: xor_rr_i16
+; CHECK: eor [[REG:w[0-9]+]], w0, w1
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
+ %1 = xor i16 %a, %b
+ ret i16 %1
+}
+
define i32 @xor_rr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: xor_rr_i32
; CHECK: eor w0, w0, w1
@@ -106,6 +248,22 @@ define i64 @xor_rr_i64(i64 %a, i64 %b) {
ret i64 %1
}
+define zeroext i8 @xor_ri_i8(i8 signext %a) {
+; CHECK-LABEL: xor_ri_i8
+; CHECK: eor [[REG:w[0-9]+]], w0, #0xf
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
+ %1 = xor i8 %a, 15
+ ret i8 %1
+}
+
+define zeroext i16 @xor_ri_i16(i16 signext %a) {
+; CHECK-LABEL: xor_ri_i16
+; CHECK: eor [[REG:w[0-9]+]], w0, #0xff
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
+ %1 = xor i16 %a, 255
+ ret i16 %1
+}
+
define i32 @xor_ri_i32(i32 %a) {
; CHECK-LABEL: xor_ri_i32
; CHECK: eor w0, w0, #0xff
@@ -120,6 +278,24 @@ define i64 @xor_ri_i64(i64 %a) {
ret i64 %1
}
+define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {
+; CHECK-LABEL: xor_rs_i8
+; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #4
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
+ %1 = shl i8 %b, 4
+ %2 = xor i8 %a, %1
+ ret i8 %2
+}
+
+define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {
+; CHECK-LABEL: xor_rs_i16
+; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #8
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
+ %1 = shl i16 %b, 8
+ %2 = xor i16 %a, %1
+ ret i16 %2
+}
+
define i32 @xor_rs_i32(i32 %a, i32 %b) {
; CHECK-LABEL: xor_rs_i32
; CHECK: eor w0, w0, w1, lsl #8
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