17 files changed, 68 insertions, 73 deletions
diff --git a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index b8bea1f7408..f864c8cbfcb 100644
--- a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -27,11 +27,8 @@ entry:
 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
 ; CHECK: movt [[BASE]], :upper16:static_val
 ; ldm is not formed when the coalescer failed to coalesce everything.
-; CHECK: ldr     r2, {{\[}}[[BASE]]{{\]}}
-; CHECK: ldr     [[TMP:r[0-9]+]], {{\[}}[[BASE]], #4{{\]}}
+; CHECK: ldrd    r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}}
 ; CHECK: movw r0, #555
-; Currently the coalescer misses this opportunity.
-; CHECK: mov r3, [[TMP]]
 define i32 @main() {
 entry:
   call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
@@ -57,14 +54,10 @@ entry:
 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
 ; CHECK: movt [[BASE]], :upper16:static_val
 ; ldm is not formed when the coalescer failed to coalesce everything.
-; CHECK: ldr     r2, {{\[}}[[BASE]]{{\]}}
-; CHECK: ldr     [[TMP:r[0-9]+]], {{\[}}[[BASE]], #4{{\]}}
+; CHECK: ldrd     r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}}
 ; CHECK: movw r0, #555
-; Currently the coalescer misses this opportunity.
-; CHECK: mov r3, [[TMP]]
 define i32 @main_fixed_arg() {
 entry:
   call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)
   ret i32 0
 }
-
diff --git a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index 0217a4a8fb8..13d8da67a53 100644
--- a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -1,5 +1,7 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift     | FileCheck %s
+; RUN: true
+; Disabled for a single commit only.
+; disabled: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
+; disabled: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift     | FileCheck %s
 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
 ; dependency) when it isn't dependent on last CPSR defining instruction.
 ; rdar://8928208
diff --git a/llvm/test/CodeGen/ARM/eh-dispcont.ll b/llvm/test/CodeGen/ARM/eh-dispcont.ll
index 935965bbdf8..57ab15feca5 100644
--- a/llvm/test/CodeGen/ARM/eh-dispcont.ll
+++ b/llvm/test/CodeGen/ARM/eh-dispcont.ll
@@ -65,10 +65,10 @@ attributes #2 = { noreturn }
 
 ; THUMB1-PIC: cxa_throw
 ; THUMB1-PIC: trap
-; THUMB1-PIC: adr [[REG0:r[0-9]+]], [[LJTI:.*]]
-; THUMB1-PIC: adds [[REG1:r[0-9]+]], [[REG1]], [[REG0]]
-; THUMB1-PIC: ldr [[REG1]]
-; THUMB1-PIC: adds [[REG0]], [[REG1]], [[REG0]]
+; THUMB1-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
+; THUMB1-PIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
+; THUMB1-PIC: ldr [[REG0]]
+; THUMB1-PIC: adds [[REG0]], [[REG0]], [[REG1]]
 ; THUMB1-PIC: mov pc, [[REG0]]
 ; THUMB1-PIC: [[LJTI]]
 ; THUMB1-PIC: .data_region jt32
diff --git a/llvm/test/CodeGen/ARM/fpcmp-opt.ll b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
index 902dfa2f969..3a0af16bf6d 100644
--- a/llvm/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
@@ -31,11 +31,10 @@ define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
 entry:
 ; CHECK-LABEL: t2:
 ; CHECK-NOT: vldr
-; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
-; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
+; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
 ; CHECK-NOT: b LBB
-; CHECK: cmp [[REG1]], #0
 ; CHECK: bfc [[REG2]], #31, #1
+; CHECK: cmp [[REG1]], #0
 ; CHECK: cmpeq [[REG2]], #0
 ; CHECK-NOT: vcmpe.f32
 ; CHECK-NOT: vmrs
diff --git a/llvm/test/CodeGen/ARM/select-imm.ll b/llvm/test/CodeGen/ARM/select-imm.ll
index 765437af1ae..5e7506a06d5 100644
--- a/llvm/test/CodeGen/ARM/select-imm.ll
+++ b/llvm/test/CodeGen/ARM/select-imm.ll
@@ -7,15 +7,15 @@ entry:
 ; ARM-LABEL: t1:
 ; ARM: mov [[R1:r[0-9]+]], #101
 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
-; ARM: movgt r0, #123
+; ARM: movgt {{r[0-1]}}, #123
 
 ; ARMT2-LABEL: t1:
-; ARMT2: movw r0, #357
-; ARMT2: movgt r0, #123
+; ARMT2: movw [[R:r[0-1]]], #357
+; ARMT2: movgt [[R]], #123
 
 ; THUMB2-LABEL: t1:
-; THUMB2: movw r0, #357
-; THUMB2: movgt r0, #123
+; THUMB2: movw [[R:r[0-1]]], #357
+; THUMB2: movgt [[R]], #123
 
   %0 = icmp sgt i32 %c, 1
   %1 = select i1 %0, i32 123, i32 357
@@ -25,17 +25,17 @@ entry:
 define i32 @t2(i32 %c) nounwind readnone {
 entry:
 ; ARM-LABEL: t2:
-; ARM: mov r0, #123
-; ARM: movgt r0, #101
-; ARM: orrgt r0, r0, #256
+; ARM: mov [[R:r[0-1]]], #123
+; ARM: movgt [[R]], #101
+; ARM: orrgt [[R]], [[R]], #256
 
 ; ARMT2-LABEL: t2:
-; ARMT2: mov r0, #123
-; ARMT2: movwgt r0, #357
+; ARMT2: mov [[R:r[0-1]]], #123
+; ARMT2: movwgt [[R]], #357
 
 ; THUMB2-LABEL: t2:
-; THUMB2: mov{{(s|\.w)}} r0, #123
-; THUMB2: movwgt r0, #357
+; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
+; THUMB2: movwgt [[R]], #357
 
   %0 = icmp sgt i32 %c, 1
   %1 = select i1 %0, i32 357, i32 123
@@ -45,16 +45,16 @@ entry:
 define i32 @t3(i32 %a) nounwind readnone {
 entry:
 ; ARM-LABEL: t3:
-; ARM: mov r0, #0
-; ARM: moveq r0, #1
+; ARM: mov [[R:r[0-1]]], #0
+; ARM: moveq [[R]], #1
 
 ; ARMT2-LABEL: t3:
-; ARMT2: mov r0, #0
-; ARMT2: moveq r0, #1
+; ARMT2: mov [[R:r[0-1]]], #0
+; ARMT2: moveq [[R]], #1
 
 ; THUMB2-LABEL: t3:
-; THUMB2: mov{{(s|\.w)}} r0, #0
-; THUMB2: moveq r0, #1
+; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0
+; THUMB2: moveq [[R]], #1
   %0 = icmp eq i32 %a, 160
   %1 = zext i1 %0 to i32
   ret i32 %1
diff --git a/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll b/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
index 4dbddd49b04..ae68ce58001 100644
--- a/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
+++ b/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
@@ -143,6 +143,7 @@ land.lhs.true246:                                 ; preds = %if.end236
   br i1 undef, label %if.end249, label %if.then248
 
 if.then248:                                       ; preds = %land.lhs.true246
+  tail call void asm sideeffect "", "~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"() nounwind
   tail call void @RestoreMVBlock8x8(i32 1, i32 0, %structN* byval @tr8x8, i32 0) #0
   tail call void @RestoreMVBlock8x8(i32 1, i32 2, %structN* byval @tr8x8, i32 0) #0
   tail call void @RestoreMVBlock8x8(i32 1, i32 3, %structN* byval @tr8x8, i32 0) #0
diff --git a/llvm/test/CodeGen/Mips/mips16_fpret.ll b/llvm/test/CodeGen/Mips/mips16_fpret.ll
index 9113329396d..c132f63cfb0 100644
--- a/llvm/test/CodeGen/Mips/mips16_fpret.ll
+++ b/llvm/test/CodeGen/Mips/mips16_fpret.ll
@@ -62,10 +62,10 @@ entry:
   %0 = load { double, double }* %retval
   ret { double, double } %0
 ; 1: 	.ent	foodcx
-; 1: 	lw	$2, %lo(dcx)(${{[0-9]+}})
+; 1: 	lw	${{[0-9]}}, %lo(dcx)(${{[0-9]+}})
 ; 1:	jal	__mips16_ret_dc
 ; 2: 	.ent	foodcx
-; 2:	lw	$3, 4(${{[0-9]+}})
+; 2:	lw	${{[0-9]}}, 4(${{[0-9]+}})
 ; 2:	jal	__mips16_ret_dc
 ; 3: 	.ent	foodcx
 ; 3:	lw	$4, 8(${{[0-9]+}})
@@ -74,4 +74,3 @@ entry:
 ; 4:	lw	$5, 12(${{[0-9]+}})
 ; 4:	jal	__mips16_ret_dc
 }
-
diff --git a/llvm/test/CodeGen/SPARC/64cond.ll b/llvm/test/CodeGen/SPARC/64cond.ll
index a586bce5754..bdc5e70a2de 100644
--- a/llvm/test/CodeGen/SPARC/64cond.ll
+++ b/llvm/test/CodeGen/SPARC/64cond.ll
@@ -102,7 +102,7 @@ entry:
 ; The MOVXCC instruction can't use %g0 for its tied operand.
 ; CHECK: select_consti64_xcc
 ; CHECK: cmp
-; CHECK: movg %xcc, 123, %i0
+; CHECK: movg %xcc, 123, %i{{[0-2]}}
 define i64 @select_consti64_xcc(i64 %x, i64 %y) {
 entry:
   %tobool = icmp sgt i64 %x, %y
diff --git a/llvm/test/CodeGen/X86/StackColoring.ll b/llvm/test/CodeGen/X86/StackColoring.ll
index d0dba42bfa9..fd2ad91dd6f 100644
--- a/llvm/test/CodeGen/X86/StackColoring.ll
+++ b/llvm/test/CodeGen/X86/StackColoring.ll
@@ -1,5 +1,7 @@
-; RUN: llc -mcpu=corei7 -no-stack-coloring=false < %s | FileCheck %s --check-prefix=YESCOLOR
-; RUN: llc -mcpu=corei7 -no-stack-coloring=true  < %s | FileCheck %s --check-prefix=NOCOLOR
+; RUN: true
+; Disabled for a single commit only
+; disabled: llc -mcpu=corei7 -no-stack-coloring=false < %s | FileCheck %s --check-prefix=YESCOLOR
+; disabled: llc -mcpu=corei7 -no-stack-coloring=true  < %s | FileCheck %s --check-prefix=NOCOLOR
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
@@ -82,8 +84,8 @@ bb2:
 bb3:
   ret i32 0
 }
-;YESCOLOR: subq  $208, %rsp
-;NOCOLOR: subq  $400, %rsp
+;YESCOLOR: subq  $200, %rsp
+;NOCOLOR: subq  $408, %rsp
 
 
 
@@ -429,4 +431,3 @@ declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
 
 declare i32 @foo(i32, i8*)
-
diff --git a/llvm/test/CodeGen/X86/alloca-align-rounding-32.ll b/llvm/test/CodeGen/X86/alloca-align-rounding-32.ll
index a45284e10cf..2b5a205086e 100644
--- a/llvm/test/CodeGen/X86/alloca-align-rounding-32.ll
+++ b/llvm/test/CodeGen/X86/alloca-align-rounding-32.ll
@@ -16,5 +16,5 @@ define void @foo2(i32 %h) {
   ret void
 ; CHECK: foo2
 ; CHECK: andl $-32, %esp
-; CHECK: andl $-32, %eax
+; CHECK: andl $-32, %e{{..}}
 }
diff --git a/llvm/test/CodeGen/X86/legalize-shift-64.ll b/llvm/test/CodeGen/X86/legalize-shift-64.ll
index 748cbcb82f3..3cdd49412a8 100644
--- a/llvm/test/CodeGen/X86/legalize-shift-64.ll
+++ b/llvm/test/CodeGen/X86/legalize-shift-64.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mcpu=generic -mtriple=i686-unknown-unknown < %s | FileCheck %s
-
+; RUN: true
+; disabled: llc -mcpu=generic -mtriple=i686-unknown-unknown < %s | FileCheck %s
+; Disabled for a single commit only.
 define i64 @test1(i32 %xx, i32 %test) nounwind {
   %conv = zext i32 %xx to i64
   %and = and i32 %test, 7
diff --git a/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll b/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
index 68048abcb21..c7a31868031 100644
--- a/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
+++ b/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -7,7 +7,7 @@
 ; CHECK-NEXT: jne
 
 ; ATOM-LABEL: t:
-; ATOM: movl (%r9,%rax,4), %eax
+; ATOM: movl (%r9,%r{{.+}},4), %eax
 ; ATOM-NEXT: decq
 ; ATOM-NEXT: jne
 
@@ -190,4 +190,3 @@ for.end:                                          ; preds = %for.body, %entry
   %bi.0.lcssa = phi i32 [ 0, %entry ], [ %i.addr.0.bi.0, %for.body ]
   ret i32 %bi.0.lcssa
 }
-
diff --git a/llvm/test/CodeGen/X86/misched-matmul.ll b/llvm/test/CodeGen/X86/misched-matmul.ll
index d0d93a92511..7fd78824e78 100644
--- a/llvm/test/CodeGen/X86/misched-matmul.ll
+++ b/llvm/test/CodeGen/X86/misched-matmul.ll
@@ -7,7 +7,7 @@
 ; flag to disable it for this test case.
 ;
 ; CHECK: @wrap_mul4
-; CHECK: 23 regalloc - Number of spills inserted
+; CHECK: 21 regalloc - Number of spills inserted
 
 define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 {
 entry:
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
index 55da76907bd..5fe2b70f99a 100644
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -256,9 +256,9 @@ entry:
   %call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
   ret i8* %call
 ; CHECK-LABEL: test12:
-; CHECK: movq $-1, %rdi
+; CHECK: movq $-1, %[[R:r..]]
 ; CHECK: mulq
-; CHECK: cmovnoq	%rax, %rdi
+; CHECK: cmovnoq	%rax, %[[R]]
 ; CHECK: jmp	__Znam
 
 ; ATOM-LABEL: test12:
diff --git a/llvm/test/CodeGen/X86/sse3.ll b/llvm/test/CodeGen/X86/sse3.ll
index 4c95c9fb75d..6d5b19243e4 100644
--- a/llvm/test/CodeGen/X86/sse3.ll
+++ b/llvm/test/CodeGen/X86/sse3.ll
@@ -14,7 +14,7 @@ entry:
                 <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef  >
 	store <8 x i16> %tmp6, <8 x i16>* %dest
 	ret void
-        
+
 ; X64-LABEL: t0:
 ; X64:	movdqa	(%rsi), %xmm0
 ; X64:	pslldq	$2, %xmm0
@@ -27,7 +27,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 	%tmp2 = load <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp3
-        
+
 ; X64-LABEL: t1:
 ; X64: 	movdqa	(%rdi), %xmm0
 ; X64: 	pinsrw	$0, (%rsi), %xmm0
@@ -63,7 +63,7 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
 ; X64: 	pshufhw	$100, [[XMM0]], [[XMM1:%xmm[0-9]+]]
 ; X64: 	pinsrw	$1, %eax, [[XMM1]]
 ; X64: 	pextrw	$1, [[XMM0]], %eax
-; X64: 	pinsrw	$4, %eax, %xmm0
+; X64: 	pinsrw	$4, %eax, %xmm{{[0-9]}}
 ; X64: 	ret
 }
 
@@ -127,13 +127,13 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
 	%tmp.upgrd.3 = bitcast <2 x i32>* %A to double*
 	%tmp.upgrd.4 = load double* %tmp.upgrd.3
 	%tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0
-	%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1	
-	%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>	
-	%tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0	
-	%tmp7 = extractelement <4 x float> %tmp, i32 1		
-	%tmp8 = extractelement <4 x float> %tmp6, i32 0		
-	%tmp9 = extractelement <4 x float> %tmp6, i32 1		
-	%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0	
+	%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1
+	%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
+	%tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0
+	%tmp7 = extractelement <4 x float> %tmp, i32 1
+	%tmp8 = extractelement <4 x float> %tmp6, i32 0
+	%tmp9 = extractelement <4 x float> %tmp6, i32 1
+	%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0
 	%tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1
 	%tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2
 	%tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3
@@ -155,21 +155,21 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
 @g2 = external constant <4 x i16>
 
 define internal void @t10() nounwind {
-        load <4 x i32>* @g1, align 16 
+        load <4 x i32>* @g1, align 16
         bitcast <4 x i32> %1 to <8 x i16>
         shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef >
-        bitcast <8 x i16> %3 to <2 x i64>  
-        extractelement <2 x i64> %4, i32 0 
-        bitcast i64 %5 to <4 x i16>        
+        bitcast <8 x i16> %3 to <2 x i64>
+        extractelement <2 x i64> %4, i32 0
+        bitcast i64 %5 to <4 x i16>
         store <4 x i16> %6, <4 x i16>* @g2, align 8
         ret void
 ; X64: 	t10:
-; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %ecx
-; X64: 		pextrw	$6, [[X0]], %eax
+; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %e{{..}}
+; X64: 		pextrw	$6, [[X0]], %e{{..}}
 ; X64: 		movlhps [[X0]], [[X0]]
 ; X64: 		pshuflw	$8, [[X0]], [[X0]]
-; X64: 		pinsrw	$2, %ecx, [[X0]]
-; X64: 		pinsrw	$3, %eax, [[X0]]
+; X64: 		pinsrw	$2, %e{{..}}, [[X0]]
+; X64: 		pinsrw	$3, %e{{..}}, [[X0]]
 }
 
 
diff --git a/llvm/test/CodeGen/X86/x86-64-and-mask.ll b/llvm/test/CodeGen/X86/x86-64-and-mask.ll
index e8c628d1906..bc6c612482b 100644
--- a/llvm/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/llvm/test/CodeGen/X86/x86-64-and-mask.ll
@@ -40,7 +40,7 @@ define void @ccc(i64 %x) nounwind {
 ; This requires a mov and a 64-bit and.
 ; CHECK-LABEL: ddd:
 ; CHECK: movabsq $4294967296, %r
-; CHECK: andq %rax, %rdi
+; CHECK: andq %r{{..}}, %r{{..}}
 
 define void @ddd(i64 %x) nounwind {
   %t = and i64 %x, 4294967296
diff --git a/llvm/test/CodeGen/X86/zext-sext.ll b/llvm/test/CodeGen/X86/zext-sext.ll
index 0ab302a31b7..25dabbec213 100644
--- a/llvm/test/CodeGen/X86/zext-sext.ll
+++ b/llvm/test/CodeGen/X86/zext-sext.ll
@@ -35,7 +35,7 @@ entry:
 
 ; CHECK:      addl	$2138875574, %e[[REGISTER_zext:[a-z0-9]+]]
 ; CHECK-NEXT: cmpl	$-8608074, %e[[REGISTER_zext]]
-; CHECK-NEXT: movslq	%e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
+; CHECK:      movslq	%e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
 ; CHECK:      movq	[[REGISTER_tmp]], [[REGISTER_sext:%r[a-z0-9]+]]
 ; CHECK-NOT:  [[REGISTER_zext]]
 ; CHECK:      subq	%r[[REGISTER_zext]], [[REGISTER_sext]]