diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir | 14 |
2 files changed, 11 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir index 124f9f519c0..234fe57b513 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir @@ -46,10 +46,10 @@ body: | %0 = COPY %sgpr2_sgpr3 %1 = COPY %vgpr2 %2 = COPY %vgpr3 - %3 = S_LOAD_DWORDX8_IMM %0, 0 - %4 = S_LOAD_DWORDX4_IMM %0, 12 - %5 = S_LOAD_DWORDX8_IMM %0, 16 - %6 = S_LOAD_DWORDX4_IMM %0, 28 + %3 = S_LOAD_DWORDX8_IMM %0, 0, 0 + %4 = S_LOAD_DWORDX4_IMM %0, 12, 0 + %5 = S_LOAD_DWORDX8_IMM %0, 16, 0 + %6 = S_LOAD_DWORDX4_IMM %0, 28, 0 undef %7.sub0 = S_MOV_B32 212739 %20 = COPY %7 %11 = COPY %20 diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir index e15da0923be..a4e77f281ea 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -mcpu=SI -run-pass none -o - %s | FileCheck %s +# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s # This test verifies that the MIR parser can parse target index operands. --- | @@ -55,15 +55,15 @@ body: | %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 + %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0 %sgpr7 = S_MOV_B32 61440 %sgpr6 = S_MOV_B32 -1 %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec @@ -85,15 +85,15 @@ body: | %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 + %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0 %sgpr7 = S_MOV_B32 61440 %sgpr6 = S_MOV_B32 -1 %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec |
