diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll | 131 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll | 26 |
2 files changed, 137 insertions, 20 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll index 139abbe1042..a2ee2bad848 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll @@ -1,12 +1,10 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-NOENV: kernarg_segment_byte_size = 0 -; HSA-OPENCL: kernarg_segment_byte_size = 32 +; HSA: kernarg_segment_byte_size = 0 ; MESA: kernarg_segment_byte_size = 16 ; HSA: s_load_dword s0, s[4:5], 0x0 @@ -17,11 +15,24 @@ define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 { ret void } +; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 + +; HSA: kernarg_segment_byte_size = 32 +; MESA: kernarg_segment_byte_size = 16 + +; HSA: s_load_dword s0, s[4:5], 0x0 +define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 { + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load = load volatile i32, i32 addrspace(4)* %cast + ret void +} + ; GCN-LABEL: {{^}}kernel_implicitarg_ptr: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-NOENV: kernarg_segment_byte_size = 112 -; HSA-OPENCL: kernarg_segment_byte_size = 144 +; HSA: kernarg_segment_byte_size = 112 ; MESA: kernarg_segment_byte_size = 464 ; HSA: s_load_dword s0, s[4:5], 0x1c @@ -32,6 +43,20 @@ define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 { ret void } +; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 + +; HSA: kernarg_segment_byte_size = 144 +; MESA: kernarg_segment_byte_size = 464 + +; HSA: s_load_dword s0, s[4:5], 0x1c +define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 { + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load = load volatile i32, i32 addrspace(4)* %cast + ret void +} + ; GCN-LABEL: {{^}}func_implicitarg_ptr: ; GCN: s_waitcnt ; MESA: s_mov_b64 s[8:9], s[6:7] @@ -43,7 +68,25 @@ define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 { ; HSA: flat_load_dword v0, v[0:1] ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_setpc_b64 -define void @func_implicitarg_ptr() #1 { +define void @func_implicitarg_ptr() #0 { + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load = load volatile i32, i32 addrspace(4)* %cast + ret void +} + +; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr: +; GCN: s_waitcnt +; MESA: s_mov_b64 s[8:9], s[6:7] +; MESA: s_mov_b32 s11, 0xf000 +; MESA: s_mov_b32 s10, -1 +; MESA: buffer_load_dword v0, off, s[8:11], 0 +; HSA: v_mov_b32_e32 v0, s6 +; HSA: v_mov_b32_e32 v1, s7 +; HSA: flat_load_dword v0, v[0:1] +; GCN-NEXT: s_waitcnt +; GCN-NEXT: s_setpc_b64 +define void @opencl_func_implicitarg_ptr() #0 { %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* %load = load volatile i32, i32 addrspace(4)* %cast @@ -52,8 +95,7 @@ define void @func_implicitarg_ptr() #1 { ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-NOENV: kernarg_segment_byte_size = 0 -; HSA-OPENCL: kernarg_segment_byte_size = 32 +; HSA: kernarg_segment_byte_size = 0 ; MESA: kernarg_segment_byte_size = 16 ; GCN: s_mov_b64 s[6:7], s[4:5] ; GCN: s_swappc_b64 @@ -62,10 +104,20 @@ define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 { ret void } +; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: kernarg_segment_byte_size = 32 +; MESA: kernarg_segment_byte_size = 16 +; GCN: s_mov_b64 s[6:7], s[4:5] +; GCN: s_swappc_b64 +define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 { + call void @func_implicitarg_ptr() + ret void +} + ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-OPENCL: kernarg_segment_byte_size = 144 -; HSA-NOENV: kernarg_segment_byte_size = 112 +; HSA: kernarg_segment_byte_size = 112 ; MESA: kernarg_segment_byte_size = 464 ; HSA: s_add_u32 s6, s4, 0x70 @@ -78,11 +130,35 @@ define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 { ret void } +; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: kernarg_segment_byte_size = 144 +; MESA: kernarg_segment_byte_size = 464 + +; HSA: s_add_u32 s6, s4, 0x70 +; MESA: s_add_u32 s6, s4, 0x1c0 + +; GCN: s_addc_u32 s7, s5, 0{{$}} +; GCN: s_swappc_b64 +define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 { + call void @func_implicitarg_ptr() + ret void +} + ; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func: ; GCN-NOT: s6 ; GCN-NOT: s7 ; GCN-NOT: s[6:7] -define void @func_call_implicitarg_ptr_func() #1 { +define void @func_call_implicitarg_ptr_func() #0 { + call void @func_implicitarg_ptr() + ret void +} + +; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func: +; GCN-NOT: s6 +; GCN-NOT: s7 +; GCN-NOT: s[6:7] +define void @opencl_func_call_implicitarg_ptr_func() #0 { call void @func_implicitarg_ptr() ret void } @@ -104,7 +180,34 @@ define void @func_call_implicitarg_ptr_func() #1 { ; HSA: flat_load_dword v0, v[0:1] ; GCN: s_waitcnt vmcnt(0) -define void @func_kernarg_implicitarg_ptr() #1 { +define void @func_kernarg_implicitarg_ptr() #0 { + %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)* + %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr + %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg + ret void +} + +; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr: +; GCN: s_waitcnt +; MESA: s_mov_b64 s[12:13], s[6:7] +; MESA: s_mov_b32 s15, 0xf000 +; MESA: s_mov_b32 s14, -1 +; MESA: buffer_load_dword v0, off, s[12:15], 0 +; HSA: v_mov_b32_e32 v0, s6 +; HSA: v_mov_b32_e32 v1, s7 +; HSA: flat_load_dword v0, v[0:1] +; MESA: s_mov_b32 s10, s14 +; MESA: s_mov_b32 s11, s15 +; MESA: buffer_load_dword v0, off, s[8:11], 0 +; HSA: v_mov_b32_e32 v0, s8 +; HSA: v_mov_b32_e32 v1, s9 +; HSA: flat_load_dword v0, v[0:1] + +; GCN: s_waitcnt vmcnt(0) +define void @opencl_func_kernarg_implicitarg_ptr() #0 { %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)* @@ -129,5 +232,5 @@ declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2 attributes #0 = { nounwind noinline } -attributes #1 = { nounwind noinline } +attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="32" } attributes #2 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll index df14bbce415..6ece8be0ec6 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll @@ -1,9 +1,6 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s -; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s -; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s -; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s ; ALL-LABEL: {{^}}test: ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 @@ -32,8 +29,7 @@ define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 { } ; ALL-LABEL: {{^}}test_implicit_alignment -; HSA-NOENV: kernarg_segment_byte_size = 10 -; HSA-OPENCL: kernarg_segment_byte_size = 48 +; HSA: kernarg_segment_byte_size = 10 ; OS-MESA3D: kernarg_segment_byte_size = 28 ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 @@ -49,6 +45,23 @@ define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x ret void } +; ALL-LABEL: {{^}}opencl_test_implicit_alignment +; HSA: kernarg_segment_byte_size = 48 +; OS-MESA3D: kernarg_segment_byte_size = 28 +; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc +; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 +; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 +; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] +; MESA: buffer_store_dword [[V_VAL]] +; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] +define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 { + %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %val = load i32, i32 addrspace(4)* %arg.ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + ; ALL-LABEL: {{^}}test_no_kernargs: ; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: s_load_dword s{{[0-9]+}}, s[4:5] @@ -66,3 +79,4 @@ declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0 attributes #0 = { nounwind readnone } attributes #1 = { nounwind } +attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="32" } |
