summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll51
-rw-r--r--llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll31
-rw-r--r--llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll41
-rw-r--r--llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll120
4 files changed, 119 insertions, 124 deletions
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll b/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
index 693a8e4e99f..c1170137c7f 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
@@ -1,38 +1,45 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m4 %s -o - | FileCheck %s --check-prefix=CHECK-M4
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m4 %s -o - | FileCheck %s --check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
define i32 @test1(i16 zeroext %z) nounwind {
; CHECK-LABEL: test1:
-; CHECK: sxth
+; CHECK-DSP: sxth
+; CHECK-NO-DSP: sxth
%r = sext i16 %z to i32
ret i32 %r
}
define i32 @test2(i8 zeroext %z) nounwind {
; CHECK-LABEL: test2:
-; CHECK: sxtb
+; CHECK-DSP: sxtb
+; CHECK-NO-DSP: sxtb
%r = sext i8 %z to i32
ret i32 %r
}
define i32 @test3(i16 signext %z) nounwind {
; CHECK-LABEL: test3:
-; CHECK: uxth
+; CHECK-DSP: uxth
+; CHECK-NO-DSP: uxth
%r = zext i16 %z to i32
ret i32 %r
}
define i32 @test4(i8 signext %z) nounwind {
; CHECK-LABEL: test4:
-; CHECK: uxtb
+; CHECK-DSP: uxtb
+; CHECK-NO-DSP: uxtb
%r = zext i8 %z to i32
ret i32 %r
}
define i32 @test5(i32 %a, i8 %b) {
; CHECK-LABEL: test5:
-; CHECK-NOT: sxtab
-; CHECK-M4: sxtab r0, r0, r1
+; CHECK-DSP: sxtab r0, r0, r1
+; CHECK-NO-DSP-NOT: sxtab
%sext = sext i8 %b to i32
%add = add i32 %a, %sext
ret i32 %add
@@ -40,8 +47,8 @@ define i32 @test5(i32 %a, i8 %b) {
define i32 @test6(i32 %a, i32 %b) {
; CHECK-LABEL: test6:
-; CHECK-NOT: sxtab
-; CHECK-M4: sxtab r0, r0, r1
+; CHECK-DSP: sxtab r0, r0, r1
+; CHECK-NO-DSP-NOT: sxtab
%shl = shl i32 %b, 24
%ashr = ashr i32 %shl, 24
%add = add i32 %a, %ashr
@@ -50,8 +57,8 @@ define i32 @test6(i32 %a, i32 %b) {
define i32 @test7(i32 %a, i16 %b) {
; CHECK-LABEL: test7:
-; CHECK-NOT: sxtah
-; CHECK-M4: sxtah r0, r0, r1
+; CHECK-DSP: sxtah r0, r0, r1
+; CHECK-NO-DSPNOT: sxtah
%sext = sext i16 %b to i32
%add = add i32 %a, %sext
ret i32 %add
@@ -59,8 +66,8 @@ define i32 @test7(i32 %a, i16 %b) {
define i32 @test8(i32 %a, i32 %b) {
; CHECK-LABEL: test8:
-; CHECK-NOT: sxtah
-; CHECK-M4: sxtah r0, r0, r1
+; CHECK-DSP: sxtah r0, r0, r1
+; CHECK-NO-DSP-NOT: sxtah
%shl = shl i32 %b, 16
%ashr = ashr i32 %shl, 16
%add = add i32 %a, %ashr
@@ -69,8 +76,8 @@ define i32 @test8(i32 %a, i32 %b) {
define i32 @test9(i32 %a, i8 %b) {
; CHECK-LABEL: test9:
-; CHECK-NOT: uxtab
-; CHECK-M4: uxtab r0, r0, r1
+; CHECK-DSP: uxtab r0, r0, r1
+; CHECK-NO-DSP-NOT: uxtab
%zext = zext i8 %b to i32
%add = add i32 %a, %zext
ret i32 %add
@@ -78,8 +85,8 @@ define i32 @test9(i32 %a, i8 %b) {
define i32 @test10(i32 %a, i32 %b) {
;CHECK-LABEL: test10:
-;CHECK-NOT: uxtab
-;CHECK-M4: uxtab r0, r0, r1
+;CHECK-DSP: uxtab r0, r0, r1
+;CHECK-NO-DSP-NOT: uxtab
%and = and i32 %b, 255
%add = add i32 %a, %and
ret i32 %add
@@ -87,8 +94,8 @@ define i32 @test10(i32 %a, i32 %b) {
define i32 @test11(i32 %a, i16 %b) {
; CHECK-LABEL: test11:
-; CHECK-NOT: uxtah
-; CHECK-M4: uxtah r0, r0, r1
+; CHECK-DSP: uxtah r0, r0, r1
+; CHECK-NO-DSP-NOT: uxtah
%zext = zext i16 %b to i32
%add = add i32 %a, %zext
ret i32 %add
@@ -96,8 +103,8 @@ define i32 @test11(i32 %a, i16 %b) {
define i32 @test12(i32 %a, i32 %b) {
;CHECK-LABEL: test12:
-;CHECK-NOT: uxtah
-;CHECK-M4: uxtah r0, r0, r1
+;CHECK-DSP: uxtah r0, r0, r1
+;CHECK-NO-DSP-NOT: uxtah
%and = and i32 %b, 65535
%add = add i32 %a, %and
ret i32 %add
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
index a4f8aa0dbd0..c4af67a2f91 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
@@ -1,18 +1,21 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2,+t2xtpk %s -o - | FileCheck %s
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-M3
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s --check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
define i32 @test0(i8 %A) {
; CHECK-LABEL: test0:
-; CHECK: sxtb r0, r0
-; CHECK-M3: sxtb r0, r0
+; CHECK-DSP: sxtb r0, r0
+; CHECK-NO-DSP: sxtb r0, r0
%B = sext i8 %A to i32
ret i32 %B
}
define signext i8 @test1(i32 %A) {
; CHECK-LABEL: test1:
-; CHECK: sbfx r0, r0, #8, #8
-; CHECK-M3: sbfx r0, r0, #8, #8
+; CHECK-DSP: sbfx r0, r0, #8, #8
+; CHECK-NO-DSP: sbfx r0, r0, #8, #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
@@ -22,8 +25,8 @@ define signext i8 @test1(i32 %A) {
define signext i32 @test2(i32 %A, i32 %X) {
; CHECK-LABEL: test2:
-; CHECK: sxtab r0, r1, r0, ror #8
-; CHECK-M3-NOT: sxtab
+; CHECK-DSP: sxtab r0, r1, r0, ror #8
+; CHECK-NO-DSP-NOT: sxtab
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
@@ -35,8 +38,8 @@ define signext i32 @test2(i32 %A, i32 %X) {
define i32 @test3(i32 %A, i32 %X) {
; CHECK-LABEL: test3:
-; CHECK: sxtah r0, r0, r1, ror #8
-; CHECK-M3-NOT: sxtah
+; CHECK-DSP: sxtah r0, r0, r1, ror #8
+; CHECK-NO-DSP-NOT: sxtah
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = sext i16 %X.trunc to i32
@@ -46,8 +49,8 @@ define i32 @test3(i32 %A, i32 %X) {
define signext i32 @test4(i32 %A, i32 %X) {
; CHECK-LABEL: test4:
-; CHECK: sxtab r0, r1, r0, ror #16
-; CHECK-M3-NOT: sxtab
+; CHECK-DSP: sxtab r0, r1, r0, ror #16
+; CHECK-NO-DSP-NOT: sxtab
%B = lshr i32 %A, 16
%C = shl i32 %A, 16
%D = or i32 %B, %C
@@ -59,8 +62,8 @@ define signext i32 @test4(i32 %A, i32 %X) {
define signext i32 @test5(i32 %A, i32 %X) {
; CHECK-LABEL: test5:
-; CHECK: sxtah r0, r1, r0, ror #24
-; CHECK-M3-NOT: sxtah
+; CHECK-DSP: sxtah r0, r1, r0, ror #24
+; CHECK-NO-DSP-NOT: sxtah
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
index 891c706972c..22740b715dc 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
@@ -1,21 +1,22 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=A8
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=M3
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
; rdar://11318438
define zeroext i8 @test1(i32 %A.u) {
; CHECK-LABEL: test1:
-; A8: uxtb r0, r0
+; CHECK-DSP: uxtb r0, r0
+; CHECK-NO-DSP: uxtb r0, r0
%B.u = trunc i32 %A.u to i8
ret i8 %B.u
}
define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
; CHECK-LABEL: test2:
-; A8: uxtab r0, r0, r1
-
-; M3: uxtb r1, r1
-; M3-NOT: uxtab
-; M3: add r0, r1
+; CHECK-DSP: uxtab r0, r0, r1
+; CHECK-NO-DSP-NOT: uxtab
%C.u = trunc i32 %B.u to i8
%D.u = zext i8 %C.u to i32
%E.u = add i32 %A.u, %D.u
@@ -24,8 +25,8 @@ define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
define zeroext i32 @test3(i32 %A.u) {
; CHECK-LABEL: test3:
-; A8: ubfx r0, r0, #8, #16
-; M3: ubfx r0, r0, #8, #16
+; CHECK-DSP: ubfx r0, r0, #8, #16
+; CHECK-NO-DSP: ubfx r0, r0, #8, #16
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u
@@ -36,8 +37,8 @@ define zeroext i32 @test3(i32 %A.u) {
define i32 @test4(i32 %A, i32 %X) {
; CHECK-LABEL: test4:
-; A8: uxtab r0, r0, r1, ror #16
-; M3-NOT: uxtab
+; CHECK-DSP: uxtab r0, r0, r1, ror #16
+; CHECK-NO-DSP-NOT: uxtab
%X.hi = lshr i32 %X, 16
%X.trunc = trunc i32 %X.hi to i8
%addend = zext i8 %X.trunc to i32
@@ -47,8 +48,8 @@ define i32 @test4(i32 %A, i32 %X) {
define i32 @test5(i32 %A, i32 %X) {
; CHECK-LABEL: test5:
-; A8: uxtah r0, r0, r1, ror #8
-; M3-NOT: uxtah
+; CHECK-DSP: uxtah r0, r0, r1, ror #8
+; CHECK-NO-DSP-NOT: uxtah
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = zext i16 %X.trunc to i32
@@ -58,8 +59,8 @@ define i32 @test5(i32 %A, i32 %X) {
define i32 @test6(i32 %A, i32 %X) {
; CHECK-LABEL: test6:
-; A8: uxtab r0, r0, r1, ror #8
-; M3-NOT: uxtab
+; CHECK-DSP: uxtab r0, r0, r1, ror #8
+; CHECK-NO-DSP-NOT: uxtab
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i8
%addend = zext i8 %X.trunc to i32
@@ -69,8 +70,8 @@ define i32 @test6(i32 %A, i32 %X) {
define i32 @test7(i32 %A, i32 %X) {
; CHECK-LABEL: test7:
-; A8: uxtah r0, r0, r1, ror #24
-; M3-NOT: uxtah
+; CHECK-DSP: uxtah r0, r0, r1, ror #24
+; CHECK-NO-DSP-NOT: uxtah
%lshr = lshr i32 %X, 24
%shl = shl i32 %X, 8
%or = or i32 %lshr, %shl
@@ -82,8 +83,8 @@ define i32 @test7(i32 %A, i32 %X) {
define i32 @test8(i32 %A, i32 %X) {
; CHECK-LABEL: test8:
-; A8: uxtah r0, r0, r1, ror #24
-; M3-NOT: uxtah
+; CHECK-DSP: uxtah r0, r0, r1, ror #24
+; CHECK-NO-DSP-NOT: uxtah
%lshr = lshr i32 %X, 24
%shl = shl i32 %X, 8
%or = or i32 %lshr, %shl
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll b/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
index b8b1bc832d9..af4532cf6f3 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -1,72 +1,63 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=ARMv7A
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=ARMv7M
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
define i32 @test1(i32 %x) {
-; ARMv7A: test1
-; ARMv7A: uxtb16 r0, r0
-
-; ARMv7M: test1
-; ARMv7M: bic r0, r0, #-16711936
+; CHECK-LABEL: test1
+; CHECK-DSP: uxtb16 r0, r0
+; CHECK-NO-DSP: bic r0, r0, #-16711936
%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
ret i32 %tmp1
}
; PR7503
define i32 @test2(i32 %x) {
-; ARMv7A: test2
-; ARMv7A: uxtb16 r0, r0, ror #8
-
-; ARMv7M: test2
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, lsr #8
+; CHECK-LABEL: test2
+; CHECK-DSP: uxtb16 r0, r0, ror #8
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test3(i32 %x) {
-; ARMv7A: test3
-; ARMv7A: uxtb16 r0, r0, ror #8
-
-; ARMv7M: test3
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, lsr #8
+; CHECK-LABEL: test3
+; CHECK-DSP: uxtb16 r0, r0, ror #8
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test4(i32 %x) {
-; ARMv7A: test4
-; ARMv7A: uxtb16 r0, r0, ror #8
-
-; ARMv7M: test4
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, lsr #8
+; CHECK-LABEL: test4
+; CHECK-DSP: uxtb16 r0, r0, ror #8
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp6
}
define i32 @test5(i32 %x) {
-; ARMv7A: test5
-; ARMv7A: uxtb16 r0, r0, ror #8
-
-; ARMv7M: test5
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, lsr #8
+; CHECK-LABEL: test5
+; CHECK-DSP: uxtb16 r0, r0, ror #8
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test6(i32 %x) {
-; ARMv7A: test6
-; ARMv7A: uxtb16 r0, r0, ror #16
-
-; ARMv7M: test6
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, ror #16
+; CHECK-LABEL: test6
+; CHECK-DSP: uxtb16 r0, r0, ror #16
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@@ -76,12 +67,10 @@ define i32 @test6(i32 %x) {
}
define i32 @test7(i32 %x) {
-; ARMv7A: test7
-; ARMv7A: uxtb16 r0, r0, ror #16
-
-; ARMv7M: test7
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, ror #16
+; CHECK-LABEL: test7
+; CHECK-DSP: uxtb16 r0, r0, ror #16
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@@ -91,12 +80,10 @@ define i32 @test7(i32 %x) {
}
define i32 @test8(i32 %x) {
-; ARMv7A: test8
-; ARMv7A: uxtb16 r0, r0, ror #24
-
-; ARMv7M: test8
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, ror #24
+; CHECK-LABEL: test8
+; CHECK-DSP: uxtb16 r0, r0, ror #24
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, ror #24
%tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
%tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
@@ -105,12 +92,10 @@ define i32 @test8(i32 %x) {
}
define i32 @test9(i32 %x) {
-; ARMv7A: test9
-; ARMv7A: uxtb16 r0, r0, ror #24
-
-; ARMv7M: test9
-; ARMv7M: mov.w r1, #16711935
-; ARMv7M: and.w r0, r1, r0, ror #24
+; CHECK-LABEL: test9
+; CHECK-DSP: uxtb16 r0, r0, ror #24
+; CHECK-NO-DSP: mov.w r1, #16711935
+; CHECK-NO-DSP: and.w r0, r1, r0, ror #24
%tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
@@ -119,19 +104,18 @@ define i32 @test9(i32 %x) {
}
define i32 @test10(i32 %p0) {
-; ARMv7A: test10
-; ARMv7A: mov.w r1, #16253176
-; ARMv7A: and.w r0, r1, r0, lsr #7
-; ARMv7A: lsrs r1, r0, #5
-; ARMv7A: uxtb16 r1, r1
-; ARMv7A: orrs r0, r1
-
-; ARMv7M: test10
-; ARMv7M: mov.w r1, #16253176
-; ARMv7M: and.w r0, r1, r0, lsr #7
-; ARMv7M: mov.w r1, #458759
-; ARMv7M: and.w r1, r1, r0, lsr #5
-; ARMv7M: orrs r0, r1
+; CHECK-LABEL: test10
+; CHECK-DSP: mov.w r1, #16253176
+; CHECK-DSP: and.w r0, r1, r0, lsr #7
+; CHECK-DSP: lsrs r1, r0, #5
+; CHECK-DSP: uxtb16 r1, r1
+; CHECk-DSP: orrs r0, r1
+
+; CHECK-NO-DSP: mov.w r1, #16253176
+; CHECK-NO-DSP: and.w r0, r1, r0, lsr #7
+; CHECK-NO-DSP: mov.w r1, #458759
+; CHECK-NO-DSP: and.w r1, r1, r0, lsr #5
+; CHECK-NO-DSP: orrs r0, r1
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
%tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]
OpenPOWER on IntegriCloud