3 files changed, 32 insertions, 43 deletions
diff --git a/llvm/test/CodeGen/AArch64/bitfield-insert.ll b/llvm/test/CodeGen/AArch64/bitfield-insert.ll
index 47aa5b09572..b67aa0fa23f 100644
--- a/llvm/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield-insert.ll
@@ -8,10 +8,7 @@
 
 define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
 ; CHECK-LABEL: from_clang:
-; CHECK-AARCH64: bfi w0, w1, #3, #4
-; CHECK-ARCH64-NEXT: ret
-
-; CHECK-ARM64: bfm {{w[0-9]+}}, {{w[0-9]+}}, #29, #3
+; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
 
 entry:
   %f.coerce.fca.0.extract = extractvalue [1 x i64] %f.coerce, 0
@@ -30,8 +27,7 @@ entry:
 define void @test_whole32(i32* %existing, i32* %new) {
 ; CHECK-LABEL: test_whole32:
 
-; CHECK-AARCH64: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
-; CHECK-ARM64: bfm {{w[0-9]+}}, {{w[0-9]+}}, #6, #4
+; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
 
   %oldval = load volatile i32* %existing
   %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
@@ -48,8 +44,7 @@ define void @test_whole32(i32* %existing, i32* %new) {
 
 define void @test_whole64(i64* %existing, i64* %new) {
 ; CHECK-LABEL: test_whole64:
-; CHECK-AARCH64: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
-; CHECK-ARM64: bfm {{x[0-9]+}}, {{x[0-9]+}}, #38, #13
+; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
 ; CHECK-NOT: and
 ; CHECK: ret
 
@@ -71,7 +66,8 @@ define void @test_whole32_from64(i64* %existing, i64* %new) {
 
 ; CHECK-AARCH64: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16
 ; CHECK-AARCH64-NOT: and
-; CHECK-ARM64: bfm {{x[0-9]+}}, {{x[0-9]+}}, #0, #15
+
+; CHECK-ARM64: bfxil {{x[0-9]+}}, {{x[0-9]+}}, #0, #16
 
 ; CHECK: ret
 
@@ -90,11 +86,9 @@ define void @test_whole32_from64(i64* %existing, i64* %new) {
 define void @test_32bit_masked(i32 *%existing, i32 *%new) {
 ; CHECK-LABEL: test_32bit_masked:
 
-; CHECK-AARCH64: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
-; CHECK-AARCH64: and {{w[0-9]+}}, [[INSERT]], #0xff
-
 ; CHECK-ARM64: and
-; CHECK-ARM64: bfm {{w[0-9]+}}, {{w[0-9]+}}, #29, #3
+; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
+; CHECK-AARCH64: and {{w[0-9]+}}, [[INSERT]], #0xff
 
   %oldval = load volatile i32* %existing
   %oldval_keep = and i32 %oldval, 135 ; = 0x87
@@ -111,11 +105,9 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) {
 
 define void @test_64bit_masked(i64 *%existing, i64 *%new) {
 ; CHECK-LABEL: test_64bit_masked:
-; CHECK-AARCH64: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
-; CHECK-AARCH64: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
-
 ; CHECK-ARM64: and
-; CHECK-ARM64: bfm {{x[0-9]+}}, {{x[0-9]+}}, #24, #7
+; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
+; CHECK-AARCH64: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
 
   %oldval = load volatile i64* %existing
   %oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000
@@ -134,11 +126,9 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) {
 define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
 ; CHECK-LABEL: test_32bit_complexmask:
 
-; CHECK-AARCH64: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
-; CHECK-AARCH64: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
-
 ; CHECK-ARM64: and
-; CHECK-ARM64: bfm {{w[0-9]+}}, {{w[0-9]+}}, #29, #3
+; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
+; CHECK-AARCH64: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
   %oldval = load volatile i32* %existing
   %oldval_keep = and i32 %oldval, 647 ; = 0x287
@@ -208,8 +198,7 @@ define void @test_32bit_with_shr(i32* %existing, i32* %new) {
   %combined = or i32 %oldval_keep, %newval_masked
   store volatile i32 %combined, i32* %existing
 ; CHECK: lsr [[BIT:w[0-9]+]], {{w[0-9]+}}, #14
-; CHECK-AARCH64: bfi {{w[0-9]+}}, [[BIT]], #26, #5
-; CHECK-ARM64: bfm {{w[0-9]+}}, [[BIT]], #6, #4
+; CHECK: bfi {{w[0-9]+}}, [[BIT]], #26, #5
 
   ret void
 }
diff --git a/llvm/test/CodeGen/ARM64/bitfield-extract.ll b/llvm/test/CodeGen/ARM64/bitfield-extract.ll
index 3ea6d938e9d..112efddd4fa 100644
--- a/llvm/test/CodeGen/ARM64/bitfield-extract.ll
+++ b/llvm/test/CodeGen/ARM64/bitfield-extract.ll
@@ -74,7 +74,7 @@ define void @fct4(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct4:
 ; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], x1, #16, #39
+; CHECK-NEXT: bfxil [[REG1]], x1, #16, #24
 ; CHECK-NEXT: str [[REG1]],
 ; CHECK-NEXT: ret
   %0 = load i64* %y, align 8
@@ -90,7 +90,7 @@ define void @fct5(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct5:
 ; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
 ; CHECK-NEXT: str [[REG1]],
 ; CHECK-NEXT: ret
   %0 = load i32* %y, align 8
@@ -107,7 +107,7 @@ define void @fct6(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct6:
 ; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
@@ -128,7 +128,7 @@ define void @fct7(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct7:
 ; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
 ; lsl is an alias of ubfm
 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
@@ -150,7 +150,7 @@ define void @fct8(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct8:
 ; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
@@ -172,7 +172,7 @@ define void @fct9(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct9:
 ; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
@@ -193,7 +193,7 @@ define void @fct10(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct10:
 ; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], w1, #0, #2
+; CHECK-NEXT: bfxil [[REG1]], w1, #0, #3
 ; lsl is an alias of ubfm
 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
@@ -213,7 +213,7 @@ define void @fct11(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct11:
 ; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], x1, #0, #2
+; CHECK-NEXT: bfxil [[REG1]], x1, #0, #3
 ; lsl is an alias of ubfm
 ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
@@ -242,7 +242,7 @@ define void @fct12(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct12:
 ; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #2, #28
 ; CHECK-NEXT: str [[REG2]],
@@ -265,7 +265,7 @@ define void @fct13(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct13:
 ; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
+; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: ubfx [[REG2:x[0-9]+]], [[REG1]], #2, #60
 ; CHECK-NEXT: str [[REG2]],
@@ -288,10 +288,10 @@ define void @fct14(i32* nocapture %y, i32 %x, i32 %x1) nounwind optsize inlinehi
 entry:
 ; CHECK-LABEL: fct14:
 ; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], w1, #16, #23
+; CHECK-NEXT: bfxil [[REG1]], w1, #16, #8
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #4
-; CHECK-NEXT: bfm [[REG2]], w2, #5, #7
+; CHECK-NEXT: bfxil [[REG2]], w2, #5, #3
 ; lsl is an alias of ubfm
 ; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2
 ; CHECK-NEXT: str [[REG3]],
@@ -318,10 +318,10 @@ define void @fct15(i64* nocapture %y, i64 %x, i64 %x1) nounwind optsize inlinehi
 entry:
 ; CHECK-LABEL: fct15:
 ; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfm [[REG1]], x1, #16, #23
+; CHECK-NEXT: bfxil [[REG1]], x1, #16, #8
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #4
-; CHECK-NEXT: bfm [[REG2]], x2, #5, #7
+; CHECK-NEXT: bfxil [[REG2]], x2, #5, #3
 ; lsl is an alias of ubfm
 ; CHECK-NEXT: lsl [[REG3:x[0-9]+]], [[REG2]], #2
 ; CHECK-NEXT: str [[REG3]],
@@ -352,7 +352,7 @@ entry:
 ; CHECK: movk [[REGCST]], #0x8160
 ; Do the masking
 ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
-; CHECK-NEXT: bfm [[REG2]], w1, #16, #18
+; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28
 ; CHECK-NEXT: str [[REG3]],
@@ -381,7 +381,7 @@ entry:
 ; CHECK: movk w[[REGCST]], #0x8160
 ; Do the masking
 ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
-; CHECK-NEXT: bfm [[REG2]], x1, #16, #18
+; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60
 ; CHECK-NEXT: str [[REG3]],
@@ -521,12 +521,12 @@ define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
   %positioned_masked_field = and i32 %positioned_field, 120
   %masked_dst = and i32 %dst, 7
   %insertion = or i32 %masked_dst, %positioned_masked_field
-; CHECK: {{bfm|bfi}}
+; CHECK: {{bfm|bfi|bfxil}}
 
   %shl16 = shl i32 %insertion, 8
   %or18 = or i32 %shl16, %insertion
   %conv19 = trunc i32 %or18 to i16
-; CHECK: {{bfm w[0-9]+, w[0-9]+, #24, #6|bfi w[0-9]+, w[0-9]+, #8, #7}}
+; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #8, #7
 
   ret i16 %conv19
 }
diff --git a/llvm/test/CodeGen/ARM64/strict-align.ll b/llvm/test/CodeGen/ARM64/strict-align.ll
index bb42780a858..2fbe47ce568 100644
--- a/llvm/test/CodeGen/ARM64/strict-align.ll
+++ b/llvm/test/CodeGen/ARM64/strict-align.ll
@@ -4,7 +4,7 @@
 define i32 @f0(i32* nocapture %p) nounwind {
 ; CHECK-STRICT: ldrh [[HIGH:w[0-9]+]], [x0, #2]
 ; CHECK-STRICT: ldrh [[LOW:w[0-9]+]], [x0]
-; CHECK-STRICT: bfm [[LOW]], [[HIGH]], #16, #15
+; CHECK-STRICT: bfi [[LOW]], [[HIGH]], #16, #16
 ; CHECK-STRICT: ret
 
 ; CHECK: ldr w0, [x0]
@@ -15,7 +15,7 @@ define i32 @f0(i32* nocapture %p) nounwind {
 
 define i64 @f1(i64* nocapture %p) nounwind {
 ; CHECK-STRICT:	ldp	w[[LOW:[0-9]+]], w[[HIGH:[0-9]+]], [x0]
-; CHECK-STRICT: bfm x[[LOW]], x[[HIGH]], #32, #31
+; CHECK-STRICT: bfi x[[LOW]], x[[HIGH]], #32, #32
 ; CHECK-STRICT:	ret
 
 ; CHECK: ldr x0, [x0]