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-rw-r--r--llvm/test/CodeGen/MSP430/shifts.ll25
1 files changed, 25 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MSP430/shifts.ll b/llvm/test/CodeGen/MSP430/shifts.ll
index 6d4050f42be..073251943d0 100644
--- a/llvm/test/CodeGen/MSP430/shifts.ll
+++ b/llvm/test/CodeGen/MSP430/shifts.ll
@@ -5,6 +5,7 @@ target triple = "msp430-elf"
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr8:
+; CHECK: clrc
; CHECK: rrc.b
%shr = lshr i8 %a, %cnt
ret i8 %shr
@@ -29,6 +30,7 @@ entry:
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr16:
+; CHECK: clrc
; CHECK: rrc
%shr = lshr i16 %a, %cnt
ret i16 %shr
@@ -49,3 +51,26 @@ entry:
%shl = shl i16 %a, %cnt
ret i16 %shl
}
+
+define i16 @ashr10_i16(i16 %a) #0 {
+entry:
+; CHECK-LABEL: ashr10_i16:
+; CHECK: swpb r12
+; CHECK-NEXT: sxt r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+ %shr = ashr i16 %a, 10
+ ret i16 %shr
+}
+
+define i16 @lshr10_i16(i16 %a) #0 {
+entry:
+; CHECK-LABEL: lshr10_i16:
+; CHECK: swpb r12
+; CHECK-NEXT: mov.b r12, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: rra r12
+ %shr = lshr i16 %a, 10
+ ret i16 %shr
+}
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