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-rw-r--r--llvm/test/CodeGen/ARM/vector-load.ll10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/vector-load.ll b/llvm/test/CodeGen/ARM/vector-load.ll
index a638c2bdb9b..ed734723a86 100644
--- a/llvm/test/CodeGen/ARM/vector-load.ll
+++ b/llvm/test/CodeGen/ARM/vector-load.ll
@@ -251,3 +251,13 @@ define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
%zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA
}
+
+; CHECK-LABEL: test_silly_load:
+; CHECK: ldr {{r[0-9]+}}, [r0, #24]
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:128]!
+; CHECK: vldr d{{[0-9]+}}, [r0]
+
+define void @test_silly_load(<28 x i8>* %addr) {
+ load volatile <28 x i8>, <28 x i8>* %addr
+ ret void
+}
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