diff options
Diffstat (limited to 'llvm/test/CodeGen')
79 files changed, 5187 insertions, 664 deletions
diff --git a/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll b/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll index fa5916aa98e..38b7d51b4a7 100644 --- a/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll +++ b/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; The instructions addis,addi, bl are used to calculate the address of TLS ; thread local variables. These TLS access code sequences are generated ; repeatedly every time the thread local variable is accessed. By communicating diff --git a/llvm/test/CodeGen/PowerPC/addegluecrash.ll b/llvm/test/CodeGen/PowerPC/addegluecrash.ll index a1d98054583..a7653735eaa 100644 --- a/llvm/test/CodeGen/PowerPC/addegluecrash.ll +++ b/llvm/test/CodeGen/PowerPC/addegluecrash.ll @@ -27,6 +27,7 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n ; CHECK-NEXT: mr 4, 10 ; CHECK-NEXT: clrldi 4, 4, 32 ; CHECK-NEXT: std 4, 0(3) +; CHECK-NEXT: std 6, -8(1) # 8-byte Folded Spill ; CHECK-NEXT: blr %1 = load i64, i64* %a, align 8 %conv = zext i64 %1 to i128 diff --git a/llvm/test/CodeGen/PowerPC/atomics-constant.ll b/llvm/test/CodeGen/PowerPC/atomics-constant.ll index 559cd9eb656..ac0b16b55f7 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-constant.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-constant.ll @@ -8,14 +8,14 @@ target triple = "powerpc64le-unknown-linux-gnu" define i64 @foo() { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: addis 3, 2, a@toc@ha ; CHECK-NEXT: li 4, 0 -; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: addi 3, 3, a@toc@l ; CHECK-NEXT: cmpd 7, 4, 4 ; CHECK-NEXT: ld 3, 0(3) +; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: bne- 7, .+4 ; CHECK-NEXT: isync -; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: blr entry: %value = load atomic i64, i64* @a acquire, align 8 diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll index 8c934ba6586..d671c76f5f4 100644 --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -1,7 +1,7 @@ -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ +; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ ; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ ; RUN: | FileCheck -check-prefix=CHECK-BE %s diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll index 6c8d5964cb3..ef433bd3e45 100644 --- a/llvm/test/CodeGen/PowerPC/f128-conv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll index d5ffea69fac..d346683d502 100644 --- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -verify-machineinstrs -enable-ppc-quad-precision \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll index 3ab5ee94142..bae676cd09c 100644 --- a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ -; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -enable-ppc-quad-precision < %s | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll index a080baedd8e..8823beb9684 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll @@ -2,7 +2,7 @@ ; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; When fastisel better supports VSX fix up this test case. ; -; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -relocation-model=pic -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 define i32 @t1(i8 signext %a) nounwind { %1 = sext i8 %a to i32 diff --git a/llvm/test/CodeGen/PowerPC/mcm-13.ll b/llvm/test/CodeGen/PowerPC/mcm-13.ll index 6f69b43194a..d7c50efbbae 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-13.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-13.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s ; Test correct code generation for medium and large code model ; for loading and storing a weak variable diff --git a/llvm/test/CodeGen/PowerPC/mcm-6.ll b/llvm/test/CodeGen/PowerPC/mcm-6.ll index b1ad8c2b43c..a8fe9c332b1 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-6.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-6.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s ; Test correct code generation for medium and large code model ; for loading and storing a tentatively defined variable. diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll index 12585c2b7fd..1b11bfd2b47 100644 --- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \ ; RUN: | FileCheck %s ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \ ; RUN: | FileCheck %s -check-prefix=CHECK-LE ; The build[csilf] functions simply test the scalar_to_vector handling with diff --git a/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll b/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll index 3b3d9add183..6c3b55d5987 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS +; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s +; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s +; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS -; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS +; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM %class.T = type { [2 x i8] } diff --git a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll index f5319b24d45..2593fa4c000 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -1,33 +1,33 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll index a35250526c7..3819e2654f2 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -1,8 +1,8 @@ -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr8 \ ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \ +; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mattr=+altivec \ ; RUN: -mattr=-vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr9 \ ; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s ; Currently VSX support is disabled for this test because we generate lxsdx diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll index 738577a412c..851942caf4c 100644 --- a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll +++ b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/pr32140.ll b/llvm/test/CodeGen/PowerPC/pr32140.ll index 3feb9bd9c9e..ddcf2723239 100644 --- a/llvm/test/CodeGen/PowerPC/pr32140.ll +++ b/llvm/test/CodeGen/PowerPC/pr32140.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE +; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE @as = common local_unnamed_addr global i16 0, align 2 @bs = common local_unnamed_addr global i16 0, align 2 @@ -10,10 +10,33 @@ define void @bswapStorei64Toi32() { ; CHECK-LABEL: bswapStorei64Toi32: ; CHECK: # %bb.0: # %entry -; CHECK: lwa 3, 0(3) +; CHECK-NEXT: addis 3, 2, ai@toc@ha +; CHECK-NEXT: addis 4, 2, bi@toc@ha +; CHECK-NEXT: lwa 3, ai@toc@l(3) +; CHECK-NEXT: addi 4, 4, bi@toc@l ; CHECK-NEXT: rldicl 3, 3, 32, 32 ; CHECK-NEXT: stwbrx 3, 0, 4 ; CHECK-NEXT: blr +; CHECK-LE-LABEL: bswapStorei64Toi32: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addis 3, 2, ai@toc@ha +; CHECK-LE-NEXT: addis 4, 2, bi@toc@ha +; CHECK-LE-NEXT: lwa 3, ai@toc@l(3) +; CHECK-LE-NEXT: addi 4, 4, bi@toc@l +; CHECK-LE-NEXT: rldicl 3, 3, 32, 32 +; CHECK-LE-NEXT: stwbrx 3, 0, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: bswapStorei64Toi32: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-BE-NEXT: addis 4, 2, .LC1@toc@ha +; CHECK-BE-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-BE-NEXT: ld 4, .LC1@toc@l(4) +; CHECK-BE-NEXT: lwa 3, 0(3) +; CHECK-BE-NEXT: rldicl 3, 3, 32, 32 +; CHECK-BE-NEXT: stwbrx 3, 0, 4 +; CHECK-BE-NEXT: blr entry: %0 = load i32, i32* @ai, align 4 %conv.i = sext i32 %0 to i64 @@ -26,10 +49,33 @@ entry: define void @bswapStorei32Toi16() { ; CHECK-LABEL: bswapStorei32Toi16: ; CHECK: # %bb.0: # %entry -; CHECK: lha 3, 0(3) +; CHECK-NEXT: addis 3, 2, as@toc@ha +; CHECK-NEXT: addis 4, 2, bs@toc@ha +; CHECK-NEXT: lha 3, as@toc@l(3) +; CHECK-NEXT: addi 4, 4, bs@toc@l ; CHECK-NEXT: srwi 3, 3, 16 ; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: blr +; CHECK-LE-LABEL: bswapStorei32Toi16: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addis 3, 2, as@toc@ha +; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha +; CHECK-LE-NEXT: lha 3, as@toc@l(3) +; CHECK-LE-NEXT: addi 4, 4, bs@toc@l +; CHECK-LE-NEXT: srwi 3, 3, 16 +; CHECK-LE-NEXT: sthbrx 3, 0, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: bswapStorei32Toi16: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha +; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4) +; CHECK-BE-NEXT: lha 3, 0(3) +; CHECK-BE-NEXT: srwi 3, 3, 16 +; CHECK-BE-NEXT: sthbrx 3, 0, 4 +; CHECK-BE-NEXT: blr entry: %0 = load i16, i16* @as, align 2 %conv.i = sext i16 %0 to i32 @@ -42,10 +88,33 @@ entry: define void @bswapStorei64Toi16() { ; CHECK-LABEL: bswapStorei64Toi16: ; CHECK: # %bb.0: # %entry -; CHECK: lha 3, 0(3) +; CHECK-NEXT: addis 3, 2, as@toc@ha +; CHECK-NEXT: addis 4, 2, bs@toc@ha +; CHECK-NEXT: lha 3, as@toc@l(3) +; CHECK-NEXT: addi 4, 4, bs@toc@l ; CHECK-NEXT: rldicl 3, 3, 16, 48 ; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: blr +; CHECK-LE-LABEL: bswapStorei64Toi16: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addis 3, 2, as@toc@ha +; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha +; CHECK-LE-NEXT: lha 3, as@toc@l(3) +; CHECK-LE-NEXT: addi 4, 4, bs@toc@l +; CHECK-LE-NEXT: rldicl 3, 3, 16, 48 +; CHECK-LE-NEXT: sthbrx 3, 0, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: bswapStorei64Toi16: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha +; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4) +; CHECK-BE-NEXT: lha 3, 0(3) +; CHECK-BE-NEXT: rldicl 3, 3, 16, 48 +; CHECK-BE-NEXT: sthbrx 3, 0, 4 +; CHECK-BE-NEXT: blr entry: %0 = load i16, i16* @as, align 2 %conv.i = sext i16 %0 to i64 diff --git a/llvm/test/CodeGen/PowerPC/preemption.ll b/llvm/test/CodeGen/PowerPC/preemption.ll index 5652f6d730a..9a0d81fbbd7 100644 --- a/llvm/test/CodeGen/PowerPC/preemption.ll +++ b/llvm/test/CodeGen/PowerPC/preemption.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple powerpc64le-unkown-gnu-linux < %s | FileCheck %s +; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \ +; RUN: < %s | FileCheck %s ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \ ; RUN: < %s | FileCheck --check-prefix=STATIC %s ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \ diff --git a/llvm/test/CodeGen/PowerPC/save-bp.ll b/llvm/test/CodeGen/PowerPC/save-bp.ll index 2e403cb80f4..8a7cef69263 100644 --- a/llvm/test/CodeGen/PowerPC/save-bp.ll +++ b/llvm/test/CodeGen/PowerPC/save-bp.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64 -; RUN: llc -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 -; RUN: llc -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC +; RUN: llc -ppc-always-use-base-pointer -relocation-model=static < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 +; RUN: llc -ppc-always-use-base-pointer -relocation-model=pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC ; CHECK-LABEL: fred: diff --git a/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll b/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll index 2018bcbbc93..01053c4070f 100644 --- a/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll +++ b/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll index ac0bcc74068..0811287a792 100644 --- a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll +++ b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll @@ -1,13 +1,13 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -O3 < %s | FileCheck %s -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ +; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ +; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -mattr=-power9-vector < %s | FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll index 4341b59390e..62d66c5747b 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll index 9623a63e9bc..2b9d0ef1faa 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll index 513caa30bc6..893b374d852 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c' @@ -17,6 +17,19 @@ define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv2 = zext i1 %cmp to i32 @@ -32,6 +45,21 @@ define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %sub = sext i1 %cmp to i32 @@ -45,6 +73,17 @@ define signext i32 @test_ieqsc_z(i8 signext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -59,6 +98,19 @@ define signext i32 @test_ieqsc_sext_z(i8 signext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %sub = sext i1 %cmp to i32 @@ -69,13 +121,30 @@ entry: define void @test_ieqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -87,14 +156,33 @@ entry: define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = sext i1 %cmp to i8 @@ -106,12 +194,27 @@ entry: define void @test_ieqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = zext i1 %cmp to i8 @@ -123,13 +226,30 @@ entry: define void @test_ieqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsc_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsc_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll index 97fd7445527..d75485fcb6f 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c' @@ -17,6 +17,19 @@ define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv = zext i1 %cmp to i32 @@ -32,6 +45,21 @@ define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %sub = sext i1 %cmp to i32 @@ -45,6 +73,17 @@ define signext i32 @test_ieqsi_z(i32 signext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -59,6 +98,19 @@ define signext i32 @test_ieqsi_sext_z(i32 signext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %sub = sext i1 %cmp to i32 @@ -69,13 +121,30 @@ entry: define void @test_ieqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv = zext i1 %cmp to i32 @@ -87,14 +156,33 @@ entry: define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %sub = sext i1 %cmp to i32 @@ -106,12 +194,27 @@ entry: define void @test_ieqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -123,13 +226,30 @@ entry: define void @test_ieqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsi_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsi_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll index bb0d6ca9867..f5627ff766d 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsll.c' @@ -17,6 +17,19 @@ define signext i32 @test_ieqsll(i64 %a, i64 %b) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv = zext i1 %cmp to i32 @@ -31,6 +44,19 @@ define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %sub = sext i1 %cmp to i32 @@ -44,6 +70,17 @@ define signext i32 @test_ieqsll_z(i64 %a) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv = zext i1 %cmp to i32 @@ -57,6 +94,17 @@ define signext i32 @test_ieqsll_sext_z(i64 %a) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %sub = sext i1 %cmp to i32 @@ -67,13 +115,30 @@ entry: define void @test_ieqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -85,13 +150,30 @@ entry: define void @test_ieqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -103,12 +185,27 @@ entry: define void @test_ieqsll_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -120,12 +217,27 @@ entry: define void @test_ieqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqsll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqsll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll index 24cee5a381e..2a5ee0c0f9d 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqss.c' @@ -17,6 +17,19 @@ define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv2 = zext i1 %cmp to i32 @@ -32,6 +45,21 @@ define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %sub = sext i1 %cmp to i32 @@ -45,6 +73,17 @@ define signext i32 @test_ieqss_z(i16 signext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -59,6 +98,19 @@ define signext i32 @test_ieqss_sext_z(i16 signext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %sub = sext i1 %cmp to i32 @@ -69,13 +121,30 @@ entry: define void @test_ieqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -87,14 +156,33 @@ entry: define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = sext i1 %cmp to i16 @@ -106,12 +194,27 @@ entry: define void @test_ieqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = zext i1 %cmp to i16 @@ -123,13 +226,30 @@ entry: define void @test_ieqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ieqss_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ieqss_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll index 4ce9747156e..18243d36619 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequc.c' @@ -17,6 +17,19 @@ define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv2 = zext i1 %cmp to i32 @@ -32,6 +45,21 @@ define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %sub = sext i1 %cmp to i32 @@ -45,6 +73,17 @@ define signext i32 @test_iequc_z(i8 zeroext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -59,6 +98,19 @@ define signext i32 @test_iequc_sext_z(i8 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %sub = sext i1 %cmp to i32 @@ -69,13 +121,30 @@ entry: define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -87,14 +156,33 @@ entry: define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = sext i1 %cmp to i8 @@ -106,12 +194,27 @@ entry: define void @test_iequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = zext i1 %cmp to i8 @@ -123,13 +226,30 @@ entry: define void @test_iequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequc_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequc_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll index a0dc89048b6..afa447525ef 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequi.c' @@ -17,6 +17,19 @@ define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv = zext i1 %cmp to i32 @@ -32,6 +45,21 @@ define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %sub = sext i1 %cmp to i32 @@ -45,6 +73,17 @@ define signext i32 @test_iequi_z(i32 zeroext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -59,6 +98,19 @@ define signext i32 @test_iequi_sext_z(i32 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %sub = sext i1 %cmp to i32 @@ -69,13 +121,30 @@ entry: define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv = zext i1 %cmp to i32 @@ -87,14 +156,33 @@ entry: define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %sub = sext i1 %cmp to i32 @@ -106,12 +194,27 @@ entry: define void @test_iequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -123,13 +226,30 @@ entry: define void @test_iequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequi_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequi_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll index 60e11e6b61c..16399715386 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequll.c' @@ -17,6 +17,19 @@ define signext i32 @test_iequll(i64 %a, i64 %b) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv = zext i1 %cmp to i32 @@ -31,6 +44,19 @@ define signext i32 @test_iequll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %sub = sext i1 %cmp to i32 @@ -44,6 +70,17 @@ define signext i32 @test_iequll_z(i64 %a) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv = zext i1 %cmp to i32 @@ -57,6 +94,17 @@ define signext i32 @test_iequll_sext_z(i64 %a) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %sub = sext i1 %cmp to i32 @@ -67,13 +115,30 @@ entry: define void @test_iequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -85,13 +150,30 @@ entry: define void @test_iequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -103,12 +185,27 @@ entry: define void @test_iequll_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -120,12 +217,27 @@ entry: define void @test_iequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll index 710eaf5e232..99b388313e1 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequs.c' @@ -17,6 +17,19 @@ define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv2 = zext i1 %cmp to i32 @@ -32,6 +45,21 @@ define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %sub = sext i1 %cmp to i32 @@ -45,6 +73,17 @@ define signext i32 @test_iequs_z(i16 zeroext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -59,6 +98,19 @@ define signext i32 @test_iequs_sext_z(i16 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %sub = sext i1 %cmp to i32 @@ -69,13 +121,30 @@ entry: define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -87,14 +156,33 @@ entry: define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = sext i1 %cmp to i16 @@ -106,12 +194,27 @@ entry: define void @test_iequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = zext i1 %cmp to i16 @@ -123,13 +226,30 @@ entry: define void @test_iequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iequs_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iequs_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll index 80152f84fc3..eb457951fb7 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -14,6 +14,19 @@ define signext i32 @test_igesc(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv2 = zext i1 %cmp to i32 @@ -27,6 +40,19 @@ define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %sub = sext i1 %cmp to i32 @@ -36,13 +62,30 @@ entry: define void @test_igesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -53,13 +96,30 @@ entry: define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv3 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll index d5a194e447f..93e6c1e1f9c 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -14,6 +14,19 @@ define signext i32 @test_igesi(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %conv = zext i1 %cmp to i32 @@ -27,6 +40,19 @@ define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %sub = sext i1 %cmp to i32 @@ -36,13 +62,30 @@ entry: define void @test_igesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %conv = zext i1 %cmp to i32 @@ -53,13 +96,30 @@ entry: define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll index 75ef396ab6b..2edbdc5bb80 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll @@ -1,10 +1,10 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define signext i32 @test_igesll(i64 %a, i64 %b) { @@ -15,6 +15,21 @@ define signext i32 @test_igesll(i64 %a, i64 %b) { ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r3, 63 +; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r3, 63 +; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv = zext i1 %cmp to i32 @@ -30,6 +45,23 @@ define signext i32 @test_igesll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r3, 63 +; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r3, 63 +; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %sub = sext i1 %cmp to i32 @@ -42,6 +74,17 @@ define signext i32 @test_igesll_z(i64 %a) { ; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv = zext i1 %cmp to i32 @@ -54,6 +97,17 @@ define signext i32 @test_igesll_sext_z(i64 %a) { ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %sub = sext i1 %cmp to i32 @@ -63,12 +117,33 @@ entry: define void @test_igesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_store: ; CHECK: # %bb.0: # %entry -; CHECK: sradi r6, r3, 63 -; CHECK: subfc r3, r4, r3 -; CHECK: rldicl r3, r4, 1, 63 -; CHECK: adde r3, r6, r3 -; CHECK: std r3 +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sradi r6, r3, 63 +; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: std r3, 0(r5) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r3, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -80,14 +155,35 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r6, r3, 63 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r3, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -98,12 +194,27 @@ entry: define void @test_igesll_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv1 = zext i1 %cmp to i64 @@ -114,12 +225,27 @@ entry: define void @test_igesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igesll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igesll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigess.ll b/llvm/test/CodeGen/PowerPC/testComparesigess.ll index 8dcdafb5b85..ac04e9e86a2 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigess.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigess.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -14,6 +14,19 @@ define signext i32 @test_igess(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igess: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igess: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv2 = zext i1 %cmp to i32 @@ -27,6 +40,19 @@ define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igess_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igess_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %sub = sext i1 %cmp to i32 @@ -36,13 +62,30 @@ entry: define void @test_igess_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igess_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igess_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -53,13 +96,30 @@ entry: define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_igess_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_igess_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv3 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll index 8009043c45d..c669d694c43 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll index 77dfc3583f1..9b5f1f43c7e 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll index 75314d708f5..c2198d10bc5 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtss.ll b/llvm/test/CodeGen/PowerPC/testComparesigtss.ll index 23ddbe30f7e..93e6ccd53bd 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtss.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtss.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll index 540b82001c2..2886130dfba 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtui.ll b/llvm/test/CodeGen/PowerPC/testComparesigtui.ll index 6fef78c6b0b..a81a1a64f61 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtui.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtus.ll b/llvm/test/CodeGen/PowerPC/testComparesigtus.ll index 07e810115f9..7beca852c16 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtus.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtus.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll index c625dca9a0e..94118d642ed 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -14,6 +14,19 @@ define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv2 = zext i1 %cmp to i32 @@ -27,6 +40,19 @@ define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %sub = sext i1 %cmp to i32 @@ -36,13 +62,30 @@ entry: define void @test_ilesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -53,13 +96,30 @@ entry: define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv3 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll index 343aa51533b..a5f2f84a5a6 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -14,6 +14,19 @@ define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %conv = zext i1 %cmp to i32 @@ -27,6 +40,19 @@ define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %sub = sext i1 %cmp to i32 @@ -36,13 +62,30 @@ entry: define void @test_ilesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %conv = zext i1 %cmp to i32 @@ -53,13 +96,30 @@ entry: define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll index bd51ad65e35..532df4c3cdb 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -15,6 +15,21 @@ define signext i32 @test_ilesll(i64 %a, i64 %b) { ; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r4, 63 +; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-BE-NEXT: subfc r3, r3, r4 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r4, 63 +; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-LE-NEXT: subfc r3, r3, r4 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv = zext i1 %cmp to i32 @@ -30,6 +45,23 @@ define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r4, 63 +; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-BE-NEXT: subfc r3, r3, r4 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r4, 63 +; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-LE-NEXT: subfc r3, r3, r4 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %sub = sext i1 %cmp to i32 @@ -43,6 +75,19 @@ define signext i32 @test_ilesll_z(i64 %a) { ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addi r4, r3, -1 +; CHECK-BE-NEXT: or r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r4, r3, -1 +; CHECK-LE-NEXT: or r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv = zext i1 %cmp to i32 @@ -56,6 +101,19 @@ define signext i32 @test_ilesll_sext_z(i64 %a) { ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addi r4, r3, -1 +; CHECK-BE-NEXT: or r3, r4, r3 +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r4, r3, -1 +; CHECK-LE-NEXT: or r3, r4, r3 +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %sub = sext i1 %cmp to i32 @@ -65,14 +123,33 @@ entry: define void @test_ilesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, 0(r5) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sradi r6, r4, 63 +; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfc r4, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: std r3, 0(r5) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r4, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r4, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -84,14 +161,35 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r6, r4, 63 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfc r4, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r4, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r4, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -102,13 +200,30 @@ entry: define void @test_ilesll_z_store(i64 %a) { ; CHECK-LABEL: test_ilesll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addi r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: or r3, r5, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: or r3, r5, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv1 = zext i1 %cmp to i64 @@ -119,13 +234,30 @@ entry: define void @test_ilesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ilesll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ilesll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addi r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: or r3, r5, r3 +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ilesll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: or r3, r5, r3 +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiless.ll b/llvm/test/CodeGen/PowerPC/testComparesiless.ll index 10e7b39dd81..45c887d21ad 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiless.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiless.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -14,6 +14,19 @@ define signext i32 @test_iless(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iless: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iless: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv2 = zext i1 %cmp to i32 @@ -27,6 +40,19 @@ define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iless_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iless_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %sub = sext i1 %cmp to i32 @@ -36,13 +62,30 @@ entry: define void @test_iless_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iless_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iless_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -53,13 +96,30 @@ entry: define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iless_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iless_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv3 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesc.ll b/llvm/test/CodeGen/PowerPC/testComparesinesc.ll index a498f644622..f5ad934409e 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesinesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesinesc.ll @@ -1,20 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define signext i32 @test_inesc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %conv2 = zext i1 %cmp to i32 @@ -23,12 +39,30 @@ entry: define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc_sext: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %sub = sext i1 %cmp to i32 @@ -37,10 +71,24 @@ entry: define signext i32 @test_inesc_z(i8 signext %a) { ; CHECK-LABEL: test_inesc_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -49,11 +97,27 @@ entry: define signext i32 @test_inesc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_inesc_sext_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %sub = sext i1 %cmp to i32 @@ -62,12 +126,34 @@ entry: define void @test_inesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: stb r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -77,13 +163,37 @@ entry: define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc_sext_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: stb r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %conv3 = sext i1 %cmp to i8 @@ -93,11 +203,31 @@ entry: define void @test_inesc_z_store(i8 signext %a) { ; CHECK-LABEL: test_inesc_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: stb r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %conv2 = zext i1 %cmp to i8 @@ -107,12 +237,34 @@ entry: define void @test_inesc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_inesc_sext_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: stb r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesc_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesc_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %conv2 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesi.ll b/llvm/test/CodeGen/PowerPC/testComparesinesi.ll index b47f6c80849..3b0fe78e99c 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesinesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesinesi.ll @@ -1,20 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define signext i32 @test_inesi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %conv = zext i1 %cmp to i32 @@ -23,12 +39,30 @@ entry: define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi_sext: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %sub = sext i1 %cmp to i32 @@ -37,10 +71,24 @@ entry: define signext i32 @test_inesi_z(i32 signext %a) { ; CHECK-LABEL: test_inesi_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -49,11 +97,27 @@ entry: define signext i32 @test_inesi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_inesi_sext_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %sub = sext i1 %cmp to i32 @@ -62,12 +126,34 @@ entry: define void @test_inesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %conv = zext i1 %cmp to i32 @@ -77,13 +163,37 @@ entry: define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi_sext_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %sub = sext i1 %cmp to i32 @@ -93,11 +203,31 @@ entry: define void @test_inesi_z_store(i32 signext %a) { ; CHECK-LABEL: test_inesi_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -107,12 +237,34 @@ entry: define void @test_inesi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_inesi_sext_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesi_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesi_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesll.ll b/llvm/test/CodeGen/PowerPC/testComparesinesll.ll index 33416a06d02..bfc0b9d3fbb 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesinesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesinesll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -15,6 +15,19 @@ define signext i32 @test_inesll(i64 %a, i64 %b) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv = zext i1 %cmp to i32 @@ -28,6 +41,19 @@ define signext i32 @test_inesll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %sub = sext i1 %cmp to i32 @@ -40,6 +66,17 @@ define signext i32 @test_inesll_z(i64 %a) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv = zext i1 %cmp to i32 @@ -52,6 +89,17 @@ define signext i32 @test_inesll_sext_z(i64 %a) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %sub = sext i1 %cmp to i32 @@ -61,13 +109,30 @@ entry: define void @test_inesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -78,13 +143,30 @@ entry: define void @test_inesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -95,12 +177,27 @@ entry: define void @test_inesll_z_store(i64 %a) { ; CHECK-LABEL: test_inesll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r5, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -111,12 +208,27 @@ entry: define void @test_inesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_inesll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_inesll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_inesll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiness.ll b/llvm/test/CodeGen/PowerPC/testComparesiness.ll index 66c95cd0d91..9e570949e12 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiness.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiness.ll @@ -1,20 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 define signext i32 @test_iness(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %conv2 = zext i1 %cmp to i32 @@ -23,12 +39,30 @@ entry: define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness_sext: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %sub = sext i1 %cmp to i32 @@ -37,10 +71,24 @@ entry: define signext i32 @test_iness_z(i16 signext %a) { ; CHECK-LABEL: test_iness_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -49,11 +97,27 @@ entry: define signext i32 @test_iness_sext_z(i16 signext %a) { ; CHECK-LABEL: test_iness_sext_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %sub = sext i1 %cmp to i32 @@ -62,12 +126,34 @@ entry: define void @test_iness_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: sth r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -77,13 +163,37 @@ entry: define void @test_iness_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness_sext_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: sth r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %conv3 = sext i1 %cmp to i16 @@ -93,11 +203,31 @@ entry: define void @test_iness_z_store(i16 signext %a) { ; CHECK-LABEL: test_iness_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: sth r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %conv2 = zext i1 %cmp to i16 @@ -107,12 +237,34 @@ entry: define void @test_iness_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_iness_sext_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: sth r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_iness_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_iness_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %conv2 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineuc.ll b/llvm/test/CodeGen/PowerPC/testComparesineuc.ll index fe91449f3c5..4e7f5c05cf6 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineuc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineuc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -15,6 +15,21 @@ define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %conv2 = zext i1 %cmp to i32 @@ -30,6 +45,23 @@ define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %sub = sext i1 %cmp to i32 @@ -43,6 +75,19 @@ define signext i32 @test_ineuc_z(i8 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -57,6 +102,21 @@ define signext i32 @test_ineuc_sext_z(i8 zeroext %a) { ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %sub = sext i1 %cmp to i32 @@ -66,14 +126,33 @@ entry: define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -85,14 +164,35 @@ define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, %b %conv3 = sext i1 %cmp to i8 @@ -103,13 +203,30 @@ entry: define void @test_ineuc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %conv2 = zext i1 %cmp to i8 @@ -120,14 +237,33 @@ entry: define void @test_ineuc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineuc_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineuc_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 %conv2 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineui.ll b/llvm/test/CodeGen/PowerPC/testComparesineui.ll index ef126270f41..e8fb3dd85be 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineui.ll @@ -1,20 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %conv = zext i1 %cmp to i32 @@ -23,12 +39,30 @@ entry: define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui_sext: -; CHECK: xor r3, r3, r4 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %sub = sext i1 %cmp to i32 @@ -37,10 +71,24 @@ entry: define signext i32 @test_ineui_z(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -49,11 +97,27 @@ entry: define signext i32 @test_ineui_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_sext_z: -; CHECK: cntlzw r3, r3 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %sub = sext i1 %cmp to i32 @@ -62,12 +126,34 @@ entry: define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %conv = zext i1 %cmp to i32 @@ -77,13 +163,37 @@ entry: define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui_sext_store: -; CHECK: xor r3, r3, r4 -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, %b %sub = sext i1 %cmp to i32 @@ -93,11 +203,31 @@ entry: define void @test_ineui_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -107,12 +237,34 @@ entry: define void @test_ineui_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_sext_z_store: -; CHECK: cntlzw r3, r3 -; CHECK: srwi r3, r3, 5 -; CHECK: xori r3, r3, 1 -; CHECK: neg r3, r3 -; CHECK: stw r3, 0(r4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineui_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineui_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineull.ll b/llvm/test/CodeGen/PowerPC/testComparesineull.ll index 7f80de420fc..e288988bdcd 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineull.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineull.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -15,6 +15,19 @@ define signext i32 @test_ineull(i64 %a, i64 %b) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv = zext i1 %cmp to i32 @@ -28,6 +41,19 @@ define signext i32 @test_ineull_sext(i64 %a, i64 %b) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %sub = sext i1 %cmp to i32 @@ -40,6 +66,17 @@ define signext i32 @test_ineull_z(i64 %a) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv = zext i1 %cmp to i32 @@ -52,6 +89,17 @@ define signext i32 @test_ineull_sext_z(i64 %a) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %sub = sext i1 %cmp to i32 @@ -61,13 +109,30 @@ entry: define void @test_ineull_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -78,13 +143,30 @@ entry: define void @test_ineull_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -95,12 +177,27 @@ entry: define void @test_ineull_z_store(i64 %a) { ; CHECK-LABEL: test_ineull_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r5, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -111,12 +208,27 @@ entry: define void @test_ineull_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ineull_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineull_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineull_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineus.ll b/llvm/test/CodeGen/PowerPC/testComparesineus.ll index 9efd5d65df6..4a2f851fa64 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineus.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineus.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -16,6 +16,21 @@ define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %conv2 = zext i1 %cmp to i32 @@ -31,6 +46,23 @@ define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %sub = sext i1 %cmp to i32 @@ -44,6 +76,19 @@ define signext i32 @test_ineus_z(i16 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %conv1 = zext i1 %cmp to i32 @@ -58,6 +103,21 @@ define signext i32 @test_ineus_sext_z(i16 zeroext %a) { ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %sub = sext i1 %cmp to i32 @@ -67,14 +127,33 @@ entry: define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -86,14 +165,35 @@ define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, %b %conv3 = sext i1 %cmp to i16 @@ -104,13 +204,30 @@ entry: define void @test_ineus_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %conv2 = zext i1 %cmp to i16 @@ -121,14 +238,33 @@ entry: define void @test_ineus_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_ineus_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_ineus_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 %conv2 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll index bdd4568c8e5..3e519edcd0c 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c' @@ -17,6 +17,19 @@ define i64 @test_lleqsc(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = zext i1 %cmp to i64 @@ -32,6 +45,21 @@ define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = sext i1 %cmp to i64 @@ -45,6 +73,17 @@ define i64 @test_lleqsc_z(i8 signext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = zext i1 %cmp to i64 @@ -59,6 +98,19 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = sext i1 %cmp to i64 @@ -69,13 +121,30 @@ entry: define void @test_lleqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -87,14 +156,33 @@ entry: define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = sext i1 %cmp to i8 @@ -106,12 +194,27 @@ entry: define void @test_lleqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = zext i1 %cmp to i8 @@ -123,13 +226,30 @@ entry: define void @test_lleqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsc_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsc_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll index 6d879c691ce..4de1d588238 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -16,6 +16,19 @@ define i64 @test_lleqsi(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv1 = zext i1 %cmp to i64 @@ -31,6 +44,21 @@ define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv1 = sext i1 %cmp to i64 @@ -44,6 +72,17 @@ define i64 @test_lleqsi_z(i32 signext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -58,6 +97,19 @@ define i64 @test_lleqsi_sext_z(i32 signext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv1 = sext i1 %cmp to i64 @@ -68,13 +120,30 @@ entry: define void @test_lleqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv = zext i1 %cmp to i32 @@ -86,14 +155,33 @@ entry: define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %sub = sext i1 %cmp to i32 @@ -105,13 +193,28 @@ entry: define void @test_lleqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr ; CHECKNEXT: blr +; CHECK-BE-LABEL: test_lleqsi_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -123,13 +226,30 @@ entry: define void @test_lleqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsi_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsi_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll index f997bd900ca..ac92d171a68 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -16,6 +16,19 @@ define i64 @test_lleqsll(i64 %a, i64 %b) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -30,6 +43,19 @@ define i64 @test_lleqsll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -43,6 +69,17 @@ define i64 @test_lleqsll_z(i64 %a) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -56,6 +93,17 @@ define i64 @test_lleqsll_sext_z(i64 %a) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = sext i1 %cmp to i64 @@ -66,13 +114,30 @@ entry: define void @test_lleqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -84,13 +149,30 @@ entry: define void @test_lleqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -102,12 +184,27 @@ entry: define void @test_lleqsll_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -119,12 +216,27 @@ entry: define void @test_lleqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqsll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqsll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll index 0c4edc33a72..d65990f9dc9 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -16,6 +16,19 @@ define i64 @test_lleqss(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = zext i1 %cmp to i64 @@ -31,6 +44,21 @@ define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = sext i1 %cmp to i64 @@ -44,6 +72,17 @@ define i64 @test_lleqss_z(i16 signext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = zext i1 %cmp to i64 @@ -58,6 +97,19 @@ define i64 @test_lleqss_sext_z(i16 signext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = sext i1 %cmp to i64 @@ -68,13 +120,30 @@ entry: define void @test_lleqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -86,14 +155,33 @@ entry: define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = sext i1 %cmp to i16 @@ -105,12 +193,27 @@ entry: define void @test_lleqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = zext i1 %cmp to i16 @@ -122,13 +225,30 @@ entry: define void @test_lleqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lleqss_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lleqss_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll index 85523f05fb8..1672d19a4a3 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -16,6 +16,19 @@ define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = zext i1 %cmp to i64 @@ -31,6 +44,21 @@ define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = sext i1 %cmp to i64 @@ -44,6 +72,17 @@ define i64 @test_llequc_z(i8 zeroext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = zext i1 %cmp to i64 @@ -58,6 +97,19 @@ define i64 @test_llequc_sext_z(i8 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = sext i1 %cmp to i64 @@ -68,13 +120,30 @@ entry: define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -86,14 +155,33 @@ entry: define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, %b %conv3 = sext i1 %cmp to i8 @@ -105,12 +193,27 @@ entry: define void @test_llequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = zext i1 %cmp to i8 @@ -122,13 +225,30 @@ entry: define void @test_llequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequc_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequc_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 %conv2 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll index cb7be180ee6..fd1d13bae7f 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -16,6 +16,19 @@ define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv1 = zext i1 %cmp to i64 @@ -31,6 +44,21 @@ define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv1 = sext i1 %cmp to i64 @@ -44,6 +72,17 @@ define i64 @test_llequi_z(i32 zeroext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -58,6 +97,19 @@ define i64 @test_llequi_sext_z(i32 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv1 = sext i1 %cmp to i64 @@ -68,13 +120,30 @@ entry: define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %conv = zext i1 %cmp to i32 @@ -86,14 +155,33 @@ entry: define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, %b %sub = sext i1 %cmp to i32 @@ -105,12 +193,27 @@ entry: define void @test_llequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -122,13 +225,30 @@ entry: define void @test_llequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequi_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequi_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll index 01136f13a4e..a42b5e4c7b7 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -16,6 +16,19 @@ define i64 @test_llequll(i64 %a, i64 %b) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -30,6 +43,19 @@ define i64 @test_llequll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -43,6 +69,17 @@ define i64 @test_llequll_z(i64 %a) { ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -56,6 +93,17 @@ define i64 @test_llequll_sext_z(i64 %a) { ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = sext i1 %cmp to i64 @@ -66,13 +114,30 @@ entry: define void @test_llequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -84,13 +149,30 @@ entry: define void @test_llequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -102,12 +184,27 @@ entry: define void @test_llequll_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzd r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -119,12 +216,27 @@ entry: define void @test_llequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r3, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r3, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll index 459df8baf46..e3dde77aba7 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -16,6 +16,19 @@ define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = zext i1 %cmp to i64 @@ -31,6 +44,21 @@ define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = sext i1 %cmp to i64 @@ -44,6 +72,17 @@ define i64 @test_llequs_z(i16 zeroext %a) { ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = zext i1 %cmp to i64 @@ -58,6 +97,19 @@ define i64 @test_llequs_sext_z(i16 zeroext %a) { ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = sext i1 %cmp to i64 @@ -68,13 +120,30 @@ entry: define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -86,14 +155,33 @@ entry: define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, %b %conv3 = sext i1 %cmp to i16 @@ -105,12 +193,27 @@ entry: define void @test_llequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = zext i1 %cmp to i16 @@ -122,13 +225,30 @@ entry: define void @test_llequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llequs_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: cntlzw r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: srwi r3, r3, 5 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llequs_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 %conv2 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll index 39499a6e895..b97da250323 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -14,6 +14,19 @@ define i64 @test_llgesc(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv3 = zext i1 %cmp to i64 @@ -27,6 +40,19 @@ define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv3 = sext i1 %cmp to i64 @@ -36,13 +62,30 @@ entry: define void @test_llgesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -53,13 +96,30 @@ entry: define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i8 %a, %b %conv3 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll index d0200001bef..cc23babc000 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -14,6 +14,19 @@ define i64 @test_llgesi(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %conv1 = zext i1 %cmp to i64 @@ -27,6 +40,19 @@ define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %conv1 = sext i1 %cmp to i64 @@ -36,13 +62,30 @@ entry: define void @test_llgesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %conv = zext i1 %cmp to i32 @@ -53,13 +96,30 @@ entry: define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i32 %a, %b %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll index f2096c28ee2..1c119b950a3 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll @@ -1,10 +1,10 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define i64 @test_llgesll(i64 %a, i64 %b) { @@ -15,6 +15,21 @@ define i64 @test_llgesll(i64 %a, i64 %b) { ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r3, 63 +; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r3, 63 +; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -30,6 +45,23 @@ define i64 @test_llgesll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r3, 63 +; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r3, 63 +; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -42,6 +74,17 @@ define i64 @test_llgesll_z(i64 %a) { ; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv1 = zext i1 %cmp to i64 @@ -54,6 +97,17 @@ define i64 @test_llgesll_sext_z(i64 %a) { ; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv1 = sext i1 %cmp to i64 @@ -63,12 +117,33 @@ entry: define void @test_llgesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_store: ; CHECK: # %bb.0: # %entry -; CHECK: sradi r6, r3, 63 -; CHECK: subfc r3, r4, r3 -; CHECK: rldicl r3, r4, 1, 63 -; CHECK: adde r3, r6, r3 -; CHECK: std r3, +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sradi r6, r3, 63 +; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: std r3, 0(r5) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r3, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -80,14 +155,35 @@ define void @test_llgesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r6, r3, 63 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfc r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r3, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -98,12 +194,27 @@ entry: define void @test_llgesll_z_store(i64 %a) { ; CHECK-LABEL: test_llgesll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv1 = zext i1 %cmp to i64 @@ -114,12 +225,27 @@ entry: define void @test_llgesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llgesll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgesll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: not r3, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgesll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: not r3, r3 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll index 71af3d34ce5..400c11bef4b 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -14,6 +14,19 @@ define i64 @test_llgess(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgess: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgess: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv3 = zext i1 %cmp to i64 @@ -27,6 +40,19 @@ define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgess_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgess_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv3 = sext i1 %cmp to i64 @@ -36,13 +62,30 @@ entry: define void @test_llgess_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgess_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgess_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -53,13 +96,30 @@ entry: define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llgess_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llgess_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sge i16 %a, %b %conv3 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll index 0dc1374374f..deb9ad5621d 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll index ba70713d61e..685026ad03d 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll index d07e85972f2..a1c8777e383 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll index 3758e8e097c..94bb1454606 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll index 575451ec7fd..1a5ad44ee08 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -15,6 +15,19 @@ define i64 @test_lllesc(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesc: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesc: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv3 = zext i1 %cmp to i64 @@ -28,6 +41,19 @@ define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesc_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesc_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv3 = sext i1 %cmp to i64 @@ -37,13 +63,30 @@ entry: define void @test_lllesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesc_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesc_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv3 = zext i1 %cmp to i8 @@ -54,13 +97,30 @@ entry: define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesc_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stb r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesc_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i8 %a, %b %conv3 = sext i1 %cmp to i8 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll index e04641d608e..9b79c1739a5 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -15,6 +15,19 @@ define i64 @test_lllesi(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesi: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesi: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %conv1 = zext i1 %cmp to i64 @@ -28,6 +41,19 @@ define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesi_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesi_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %conv1 = sext i1 %cmp to i64 @@ -37,13 +63,30 @@ entry: define void @test_lllesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesi_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesi_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %conv = zext i1 %cmp to i32 @@ -54,13 +97,30 @@ entry: define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesi_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: stw r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesi_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %sub = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll index b5c340d7d58..83ce2f812ae 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -16,6 +16,21 @@ define i64 @test_lllesll(i64 %a, i64 %b) { ; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r4, 63 +; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-BE-NEXT: subfc r3, r3, r4 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r4, 63 +; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-LE-NEXT: subfc r3, r3, r4 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -32,6 +47,23 @@ define i64 @test_lllesll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r5, r4, 63 +; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-BE-NEXT: subfc r3, r3, r4 +; CHECK-BE-NEXT: adde r3, r5, r6 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r5, r4, 63 +; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 +; CHECK-LE-NEXT: subfc r3, r3, r4 +; CHECK-LE-NEXT: adde r3, r5, r6 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -46,6 +78,19 @@ define i64 @test_lllesll_z(i64 %a) { ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addi r4, r3, -1 +; CHECK-BE-NEXT: or r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r4, r3, -1 +; CHECK-LE-NEXT: or r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv1 = zext i1 %cmp to i64 @@ -60,6 +105,19 @@ define i64 @test_lllesll_sext_z(i64 %a) { ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addi r4, r3, -1 +; CHECK-BE-NEXT: or r3, r4, r3 +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r4, r3, -1 +; CHECK-LE-NEXT: or r3, r4, r3 +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv1 = sext i1 %cmp to i64 @@ -70,14 +128,33 @@ entry: define void @test_lllesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, 0(r5) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sradi r6, r4, 63 +; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfc r4, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: std r3, 0(r5) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r4, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r4, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -90,14 +167,35 @@ define void @test_lllesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sradi r6, r4, 63 +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfc r4, r3, r4 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: adde r3, r6, r3 +; CHECK-BE-NEXT: neg r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sradi r6, r4, 63 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfc r4, r3, r4 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: adde r3, r6, r3 +; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -109,13 +207,30 @@ entry: define void @test_lllesll_z_store(i64 %a) { ; CHECK-LABEL: test_lllesll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addi r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: or r3, r5, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: or r3, r5, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv1 = zext i1 %cmp to i64 @@ -127,13 +242,30 @@ entry: define void @test_lllesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lllesll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_lllesll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addi r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: or r3, r5, r3 +; CHECK-BE-NEXT: sradi r3, r3, 63 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_lllesll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addi r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: or r3, r5, r3 +; CHECK-LE-NEXT: sradi r3, r3, 63 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllless.ll b/llvm/test/CodeGen/PowerPC/testComparesllless.ll index 1f066524cc4..6f8657dac4b 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllless.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllless.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -15,6 +15,19 @@ define i64 @test_llless(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llless: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llless: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv3 = zext i1 %cmp to i64 @@ -28,6 +41,19 @@ define i64 @test_llless_sext(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llless_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llless_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv3 = sext i1 %cmp to i64 @@ -37,13 +63,30 @@ entry: define void @test_llless_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llless_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: xori r3, r3, 1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llless_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: xori r3, r3, 1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv3 = zext i1 %cmp to i16 @@ -54,13 +97,30 @@ entry: define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llless_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: sub r3, r4, r3 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-BE-NEXT: addi r3, r3, -1 +; CHECK-BE-NEXT: sth r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llless_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: sub r3, r4, r3 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 +; CHECK-LE-NEXT: addi r3, r3, -1 +; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp sle i16 %a, %b %conv3 = sext i1 %cmp to i16 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll index e785942b3c9..126d110d04c 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll index 47545e94bff..10bff2f7d94 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -15,6 +15,19 @@ define i64 @test_llnesll(i64 %a, i64 %b) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -28,6 +41,19 @@ define i64 @test_llnesll_sext(i64 %a, i64 %b) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -40,6 +66,17 @@ define i64 @test_llnesll_z(i64 %a) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -52,6 +89,17 @@ define i64 @test_llnesll_sext_z(i64 %a) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = sext i1 %cmp to i64 @@ -61,13 +109,30 @@ entry: define void @test_llnesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -78,13 +143,30 @@ entry: define void @test_llnesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -95,12 +177,27 @@ entry: define void @test_llnesll_z_store(i64 %a) { ; CHECK-LABEL: test_llnesll_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r5, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -111,12 +208,27 @@ entry: define void @test_llnesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llnesll_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llnesll_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llnesll_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllneull.ll b/llvm/test/CodeGen/PowerPC/testComparesllneull.ll index b2c5086fcba..9e6be97e8c1 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllneull.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllneull.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -15,6 +15,19 @@ define i64 @test_llneull(i64 %a, i64 %b) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -28,6 +41,19 @@ define i64 @test_llneull_sext(i64 %a, i64 %b) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_sext: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_sext: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -40,6 +66,17 @@ define i64 @test_llneull_z(i64 %a) { ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addic r4, r3, -1 +; CHECK-BE-NEXT: subfe r3, r4, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -52,6 +89,17 @@ define i64 @test_llneull_sext_z(i64 %a) { ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_sext_z: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_sext_z: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = sext i1 %cmp to i64 @@ -61,13 +109,30 @@ entry: define void @test_llneull_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: addic r4, r3, -1 +; CHECK-LE-NEXT: subfe r3, r4, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = zext i1 %cmp to i64 @@ -78,13 +143,30 @@ entry: define void @test_llneull_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_sext_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_sext_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-BE-NEXT: xor r3, r3, r4 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_sext_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r5) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, %b %conv1 = sext i1 %cmp to i64 @@ -95,12 +177,27 @@ entry: define void @test_llneull_z_store(i64 %a) { ; CHECK-LABEL: test_llneull_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: addic r5, r3, -1 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r5, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: addic r5, r3, -1 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r5, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = zext i1 %cmp to i64 @@ -111,12 +208,27 @@ entry: define void @test_llneull_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llneull_sext_z_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: blr +; CHECK-BE-LABEL: test_llneull_sext_z_store: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-BE-NEXT: subfic r3, r3, 0 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-BE-NEXT: subfe r3, r3, r3 +; CHECK-BE-NEXT: std r3, 0(r4) +; CHECK-BE-NEXT: blr +; +; CHECK-LE-LABEL: test_llneull_sext_z_store: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: subfic r3, r3, 0 +; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha +; CHECK-LE-NEXT: subfe r3, r3, r3 +; CHECK-LE-NEXT: std r3, glob@toc@l(r4) +; CHECK-LE-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 %conv1 = sext i1 %cmp to i64 diff --git a/llvm/test/CodeGen/PowerPC/toc-float.ll b/llvm/test/CodeGen/PowerPC/toc-float.ll index 4f5c34110ea..ff892e07c72 100644 --- a/llvm/test/CodeGen/PowerPC/toc-float.ll +++ b/llvm/test/CodeGen/PowerPC/toc-float.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s +; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s ; As the constant could be represented as float, a float is ; loaded from constant pool. diff --git a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll index 4d45e6e42eb..d09b2146e72 100644 --- a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9 diff --git a/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll b/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll index e8fe9dbaa45..90a928a90d0 100644 --- a/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll +++ b/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" { ; CHECK-LABEL: .Ltmp0: |
