diff options
Diffstat (limited to 'llvm/test/CodeGen')
23 files changed, 96 insertions, 65 deletions
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll index 61bbfc20135..91921d5aa3b 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll @@ -1,7 +1,8 @@ ; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s +; RUN: not llc -mtriple=arm64-none-linux-gnu -o - %s define void @foo() { ; Out of range immediate for I. - call void asm sideeffect "add x0, x0, $0", "I"(i32 4096) + call void asm sideeffect "add x0, x0, $0", "I"(i32 4097) ret void } diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll index 40746e1528c..cc4558fa54e 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll @@ -1,4 +1,5 @@ ; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s +; RUN: not llc -mtriple=arm64-apple-ios7.0 -o - %s define void @foo() { ; 32-bit bitpattern ending in 1101 can't be produced. diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll index 2c5338191fd..82006339248 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll @@ -1,4 +1,5 @@ ; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s +; RUN: not llc -mtriple=arm64-none-linux-gnu -o - %s define void @foo() { ; 32-bit bitpattern ending in 1101 can't be produced. diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll index d82d5a2ee4d..e7b8173f6ab 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll @@ -1,4 +1,5 @@ ; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s +; RUN: not llc -mtriple=arm64-apple-ios7.0 -o - %s define void @foo() { ; 32-bit bitpattern ending in 1101 can't be produced. diff --git a/llvm/test/CodeGen/AArch64/logical-imm.ll b/llvm/test/CodeGen/AArch64/logical-imm.ll index e04bb510ebf..3ae63ad16f6 100644 --- a/llvm/test/CodeGen/AArch64/logical-imm.ll +++ b/llvm/test/CodeGen/AArch64/logical-imm.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s @var32 = global i32 0 @var64 = global i64 0 diff --git a/llvm/test/CodeGen/AArch64/movw-consts.ll b/llvm/test/CodeGen/AArch64/movw-consts.ll index 38e37db7b58..e783b988b56 100644 --- a/llvm/test/CodeGen/AArch64/movw-consts.ll +++ b/llvm/test/CodeGen/AArch64/movw-consts.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64 +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64 define i64 @test0() { ; CHECK-LABEL: test0: @@ -9,43 +10,50 @@ define i64 @test0() { define i64 @test1() { ; CHECK-LABEL: test1: -; CHECK: movz x0, #1 +; CHECK-AARCH64: movz x0, #1 +; CHECK-ARM64: orr w0, wzr, #0x1 ret i64 1 } define i64 @test2() { ; CHECK-LABEL: test2: -; CHECK: movz x0, #65535 +; CHECK-AARCH64: movz x0, #65535 +; CHECK-ARM64: orr w0, wzr, #0xffff ret i64 65535 } define i64 @test3() { ; CHECK-LABEL: test3: -; CHECK: movz x0, #1, lsl #16 +; CHECK-AARCH64: movz x0, #1, lsl #16 +; CHECK-ARM64: orr w0, wzr, #0x10000 ret i64 65536 } define i64 @test4() { ; CHECK-LABEL: test4: -; CHECK: movz x0, #65535, lsl #16 +; CHECK-AARCH64: movz x0, #65535, lsl #16 +; CHECK-ARM64: orr w0, wzr, #0xffff0000 ret i64 4294901760 } define i64 @test5() { ; CHECK-LABEL: test5: -; CHECK: movz x0, #1, lsl #32 +; CHECK-AARCH64: movz x0, #1, lsl #32 +; CHECK-ARM64: orr x0, xzr, #0x100000000 ret i64 4294967296 } define i64 @test6() { ; CHECK-LABEL: test6: -; CHECK: movz x0, #65535, lsl #32 +; CHECK-AARCH64: movz x0, #65535, lsl #32 +; CHECK-ARM64: orr x0, xzr, #0xffff00000000 ret i64 281470681743360 } define i64 @test7() { ; CHECK-LABEL: test7: -; CHECK: movz x0, #1, lsl #48 +; CHECK-AARCH64: movz x0, #1, lsl #48 +; CHECK-ARM64: orr x0, xzr, #0x1000000000000 ret i64 281474976710656 } @@ -75,35 +83,40 @@ define i64 @test10() { define void @test11() { ; CHECK-LABEL: test11: -; CHECK: mov {{w[0-9]+}}, wzr +; CHECK-AARCH64: mov {{w[0-9]+}}, wzr +; CHECK-ARM64: str wzr store i32 0, i32* @var32 ret void } define void @test12() { ; CHECK-LABEL: test12: -; CHECK: movz {{w[0-9]+}}, #1 +; CHECK-AARCH64: movz {{w[0-9]+}}, #1 +; CHECK-ARM64: orr {{w[0-9]+}}, wzr, #0x1 store i32 1, i32* @var32 ret void } define void @test13() { ; CHECK-LABEL: test13: -; CHECK: movz {{w[0-9]+}}, #65535 +; CHECK-AARCH64: movz {{w[0-9]+}}, #65535 +; CHECK-ARM64: orr {{w[0-9]+}}, wzr, #0xffff store i32 65535, i32* @var32 ret void } define void @test14() { ; CHECK-LABEL: test14: -; CHECK: movz {{w[0-9]+}}, #1, lsl #16 +; CHECK-AARCH64: movz {{w[0-9]+}}, #1, lsl #16 +; CHECK-ARM64: orr {{w[0-9]+}}, wzr, #0x10000 store i32 65536, i32* @var32 ret void } define void @test15() { ; CHECK-LABEL: test15: -; CHECK: movz {{w[0-9]+}}, #65535, lsl #16 +; CHECK-AARCH64: movz {{w[0-9]+}}, #65535, lsl #16 +; CHECK-ARM64: orr {{w[0-9]+}}, wzr, #0xffff0000 store i32 4294901760, i32* @var32 ret void } @@ -119,6 +132,7 @@ define i64 @test17() { ; CHECK-LABEL: test17: ; Mustn't MOVN w0 here. -; CHECK: movn x0, #2 +; CHECK-AARCH64: movn x0, #2 +; CHECK-ARM64: orr x0, xzr, #0xfffffffffffffffd ret i64 -3 } diff --git a/llvm/test/CodeGen/AArch64/movw-shift-encoding.ll b/llvm/test/CodeGen/AArch64/movw-shift-encoding.ll index ec133bd706b..8a0da4cb932 100644 --- a/llvm/test/CodeGen/AArch64/movw-shift-encoding.ll +++ b/llvm/test/CodeGen/AArch64/movw-shift-encoding.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=aarch64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s --check-prefix=CHECK-AARCH64 +; RUN: llc -mtriple=arm64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s --check-prefix=CHECK-ARM64 @var = global i32 0 @@ -7,8 +8,13 @@ define i32* @get_var() { ret i32* @var -; CHECK: movz x0, #:abs_g3:var // encoding: [A,A,0xe0'A',0xd2'A'] -; CHECK: movk x0, #:abs_g2_nc:var // encoding: [A,A,0xc0'A',0xf2'A'] -; CHECK: movk x0, #:abs_g1_nc:var // encoding: [A,A,0xa0'A',0xf2'A'] -; CHECK: movk x0, #:abs_g0_nc:var // encoding: [A,A,0x80'A',0xf2'A'] +; CHECK-AARCH64: movz x0, #:abs_g3:var // encoding: [A,A,0xe0'A',0xd2'A'] +; CHECK-AARCH64: movk x0, #:abs_g2_nc:var // encoding: [A,A,0xc0'A',0xf2'A'] +; CHECK-AARCH64: movk x0, #:abs_g1_nc:var // encoding: [A,A,0xa0'A',0xf2'A'] +; CHECK-AARCH64: movk x0, #:abs_g0_nc:var // encoding: [A,A,0x80'A',0xf2'A'] + +; CHECK-ARM64: movz x0, #:abs_g3:var // encoding: [0bAAA00000,A,0b111AAAAA,0xd2] +; CHECK-ARM64: movk x0, #:abs_g2_nc:var // encoding: [0bAAA00000,A,0b110AAAAA,0xf2] +; CHECK-ARM64: movk x0, #:abs_g1_nc:var // encoding: [0bAAA00000,A,0b101AAAAA,0xf2] +; CHECK-ARM64: movk x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xf2] } diff --git a/llvm/test/CodeGen/AArch64/mul-lohi.ll b/llvm/test/CodeGen/AArch64/mul-lohi.ll index f58c59810ea..e9493efe8fd 100644 --- a/llvm/test/CodeGen/AArch64/mul-lohi.ll +++ b/llvm/test/CodeGen/AArch64/mul-lohi.ll @@ -1,5 +1,6 @@ ; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s ; RUN: llc -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck --check-prefix=CHECK-BE %s +; RUN: llc -mtriple=arm64-apple-ios7.0 %s -o - | FileCheck %s define i128 @test_128bitmul(i128 %lhs, i128 %rhs) { ; CHECK-LABEL: test_128bitmul: diff --git a/llvm/test/CodeGen/AArch64/ragreedy-csr.ll b/llvm/test/CodeGen/AArch64/ragreedy-csr.ll index 18a948b7872..20e1b30d74d 100644 --- a/llvm/test/CodeGen/AArch64/ragreedy-csr.ll +++ b/llvm/test/CodeGen/AArch64/ragreedy-csr.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -regalloc=greedy -regalloc-csr-first-time-cost=15 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -regalloc=greedy -regalloc-csr-first-time-cost=15 | FileCheck %s ; This testing case is reduced from 197.parser prune_match function. ; We make sure that we do not use callee-saved registers (x19 to x25). @@ -6,14 +7,14 @@ ; CHECK-LABEL: prune_match: ; CHECK: entry -; CHECK: str x30, [sp +; CHECK: {{str x30|stp x29, x30}}, [sp ; CHECK-NOT: stp x25, ; CHECK-NOT: stp x23, x24 ; CHECK-NOT: stp x21, x22 ; CHECK-NOT: stp x19, x20 ; CHECK: if.end ; CHECK: return -; CHECK: ldr x30, [sp +; CHECK: {{ldr x30|ldp x29, x30}}, [sp ; CHECK-NOT: ldp x19, x20 ; CHECK-NOT: ldp x21, x22 ; CHECK-NOT: ldp x23, x24 diff --git a/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll b/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll index 9655f90d826..7f3ba7276b5 100644 --- a/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll +++ b/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-ios7.0 -verify-machineinstrs < %s | FileCheck %s ; CallingConv.td requires a bitcast for vector arguments. Make sure we're ; actually capable of that (the test was omitted from LowerFormalArguments). diff --git a/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll b/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll index cb8432a7e4e..5c2142aeeeb 100644 --- a/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll +++ b/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s +; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -o - %s ; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB, ; causing a crash during live range calc. diff --git a/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll b/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll index 053249c6855..4a6ad55b679 100644 --- a/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll +++ b/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s @var = global void()* zeroinitializer declare void @bar() diff --git a/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll b/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll index a013a450e92..1f8ad4503c4 100644 --- a/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll +++ b/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefix CHECK-AARCH64 +; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix CHECK-ARM64 ; When generating DAG selection tables, TableGen used to only flag an ; instruction as needing a chain on its own account if it had a built-in pattern @@ -12,25 +13,32 @@ declare void @bar(i8*) define i64 @test_chains() { -; CHECK-LABEL: test_chains: +; CHECK-AARCH64-LABEL: test_chains: +; CHECK-ARM64-LABEL: test_chains: %locvar = alloca i8 call void @bar(i8* %locvar) -; CHECK: bl bar +; CHECK: bl {{_?bar}} %inc.1 = load i8* %locvar %inc.2 = zext i8 %inc.1 to i64 %inc.3 = add i64 %inc.2, 1 %inc.4 = trunc i64 %inc.3 to i8 store i8 %inc.4, i8* %locvar -; CHECK: ldrb {{w[0-9]+}}, [sp, [[LOCADDR:#[0-9]+]]] -; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1 -; CHECK: strb {{w[0-9]+}}, [sp, [[LOCADDR]]] -; CHECK: ldrb {{w[0-9]+}}, [sp, [[LOCADDR]]] +; CHECK-AARCH64: ldrb {{w[0-9]+}}, [sp, [[LOCADDR:#[0-9]+]]] +; CHECK-AARCH64: add {{w[0-9]+}}, {{w[0-9]+}}, #1 +; CHECK-AARCH64: strb {{w[0-9]+}}, [sp, [[LOCADDR]]] +; CHECK-AARCH64: ldrb {{w[0-9]+}}, [sp, [[LOCADDR]]] + +; CHECK-ARM64: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]] +; CHECK-ARM64: add {{w[0-9]+}}, {{w[0-9]+}}, #1 +; CHECK-ARM64: sturb {{w[0-9]+}}, [x29, [[LOCADDR]]] +; CHECK-ARM64: ldurb {{w[0-9]+}}, [x29, [[LOCADDR]]] %ret.1 = load i8* %locvar %ret.2 = zext i8 %ret.1 to i64 ret i64 %ret.2 -; CHECK: ret +; CHECK-AARCH64: ret +; CHECK-ARM64: ret } diff --git a/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll index 0ef981819ec..cfd94e1503b 100644 --- a/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll +++ b/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll @@ -1,26 +1,12 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-fp-elim < %s | FileCheck %s +; RUN: llc -mtriple=arm64-none-linux-gnu -disable-fp-elim < %s | FileCheck %s @var = global i32 0 declare void @bar() define void @test_w29_reserved() { ; CHECK-LABEL: test_w29_reserved: -; CHECK: .cfi_startproc -; CHECK: .cfi_def_cfa sp, 96 ; CHECK: add x29, sp, #{{[0-9]+}} -; CHECK: .cfi_def_cfa x29, 16 -; CHECK: .cfi_offset x30, -8 -; CHECK: .cfi_offset x29, -16 -; CHECK: .cfi_offset x28, -24 -; CHECK: .cfi_offset x27, -32 -; CHECK: .cfi_offset x26, -40 -; CHECK: .cfi_offset x25, -48 -; CHECK: .cfi_offset x24, -56 -; CHECK: .cfi_offset x23, -64 -; CHECK: .cfi_offset x22, -72 -; CHECK: .cfi_offset x21, -80 -; CHECK: .cfi_offset x20, -88 -; CHECK: .cfi_offset x19, -96 %val1 = load volatile i32* @var %val2 = load volatile i32* @var diff --git a/llvm/test/CodeGen/AArch64/returnaddr.ll b/llvm/test/CodeGen/AArch64/returnaddr.ll index c85f9ec4ffd..3f7edcbaa89 100644 --- a/llvm/test/CodeGen/AArch64/returnaddr.ll +++ b/llvm/test/CodeGen/AArch64/returnaddr.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s define i8* @rt0(i32 %x) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll b/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll index bd79685d34b..21c2688ca70 100644 --- a/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll +++ b/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -o - %s | FileCheck %s ; Most important point here is that the promotion of the i1 works ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output, diff --git a/llvm/test/CodeGen/AArch64/sincos-expansion.ll b/llvm/test/CodeGen/AArch64/sincos-expansion.ll index 4cd44494d54..1498eb53625 100644 --- a/llvm/test/CodeGen/AArch64/sincos-expansion.ll +++ b/llvm/test/CodeGen/AArch64/sincos-expansion.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s define float @test_sincos_f32(float %f) { %sin = call float @sinf(float %f) readnone diff --git a/llvm/test/CodeGen/AArch64/sincospow-vector-expansion.ll b/llvm/test/CodeGen/AArch64/sincospow-vector-expansion.ll index 259a55ecd0d..baa73a3c716 100644 --- a/llvm/test/CodeGen/AArch64/sincospow-vector-expansion.ll +++ b/llvm/test/CodeGen/AArch64/sincospow-vector-expansion.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s +; RUN: llc -o - %s -verify-machineinstrs -mtriple=arm64-linux-gnu -mattr=+neon | FileCheck %s define <2 x float> @test_cos_v2f64(<2 x double> %v1) { diff --git a/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll b/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll index b5d7d893844..80ed2181c4c 100644 --- a/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll +++ b/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=aarch64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s +; arm64 has its own copy of this file, copied during implementation. ; If the .tlsdesccall and blr parts are emitted completely separately (even with ; glue) then LLVM will separate them quite happily (with a spill at O0, hence diff --git a/llvm/test/CodeGen/AArch64/tls-dynamics.ll b/llvm/test/CodeGen/AArch64/tls-dynamics.ll index 68c481ce98b..0fb84c823bc 100644 --- a/llvm/test/CodeGen/AArch64/tls-dynamics.ll +++ b/llvm/test/CodeGen/AArch64/tls-dynamics.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s - +; arm64 has its own tls-dynamics.ll, copied from this one during implementation. @general_dynamic_var = external thread_local global i32 define i32 @test_generaldynamic() { @@ -10,8 +10,8 @@ define i32 @test_generaldynamic() { ret i32 %val ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var -; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:general_dynamic_var +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:general_dynamic_var] ; CHECK: .tlsdesccall general_dynamic_var ; CHECK-NEXT: blr [[CALLEE]] @@ -31,8 +31,8 @@ define i32* @test_generaldynamic_addr() { ret i32* @general_dynamic_var ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var -; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:general_dynamic_var +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:general_dynamic_var] ; CHECK: .tlsdesccall general_dynamic_var ; CHECK-NEXT: blr [[CALLEE]] @@ -55,8 +55,8 @@ define i32 @test_localdynamic() { ret i32 %val ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:_TLS_MODULE_BASE_] ; CHECK: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] @@ -78,8 +78,8 @@ define i32* @test_localdynamic_addr() { ret i32* @local_dynamic_var ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:_TLS_MODULE_BASE_] ; CHECK: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] @@ -110,8 +110,8 @@ define i32 @test_localdynamic_deduplicate() { ret i32 %sum ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], {{#?}}:tlsdesc_lo12:_TLS_MODULE_BASE_] ; CHECK: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] diff --git a/llvm/test/CodeGen/AArch64/tls-execs.ll b/llvm/test/CodeGen/AArch64/tls-execs.ll index 39ceb9a4795..61600380c24 100644 --- a/llvm/test/CodeGen/AArch64/tls-execs.ll +++ b/llvm/test/CodeGen/AArch64/tls-execs.ll @@ -1,5 +1,6 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s +; arm64 has its own copy of tls-execs.ll, copied from this one during implementation. @initial_exec_var = external thread_local(initialexec) global i32 diff --git a/llvm/test/CodeGen/AArch64/tst-br.ll b/llvm/test/CodeGen/AArch64/tst-br.ll index 154bc08c144..b6e2b19fb84 100644 --- a/llvm/test/CodeGen/AArch64/tst-br.ll +++ b/llvm/test/CodeGen/AArch64/tst-br.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s ; We've got the usual issues with LLVM reordering blocks here. The ; tests are correct for the current order, but who knows when that @@ -15,7 +16,7 @@ define i32 @test_tbz() { %tbit0 = and i32 %val, 32768 %tst0 = icmp ne i32 %tbit0, 0 br i1 %tst0, label %test1, label %end1 -; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.LBB0_[0-9]+]] +; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]] test1: %tbit1 = and i32 %val, 4096 @@ -27,22 +28,22 @@ test2: %tbit2 = and i64 %val64, 32768 %tst2 = icmp ne i64 %tbit2, 0 br i1 %tst2, label %test3, label %end1 -; CHECK: tbz {{x[0-9]+}}, #15, [[LBL_end1]] +; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]] test3: %tbit3 = and i64 %val64, 4096 %tst3 = icmp ne i64 %tbit3, 0 br i1 %tst3, label %end2, label %end1 -; CHECK: tbz {{x[0-9]+}}, #12, [[LBL_end1]] +; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]] end2: -; CHECK: movz x0, #1 +; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}} ; CHECK-NEXT: ret ret i32 1 end1: ; CHECK: [[LBL_end1]]: -; CHECK-NEXT: mov x0, xzr +; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}} ; CHECK-NEXT: ret ret i32 0 } diff --git a/llvm/test/CodeGen/AArch64/zero-reg.ll b/llvm/test/CodeGen/AArch64/zero-reg.ll index 9b1e52770ce..c4073cba08d 100644 --- a/llvm/test/CodeGen/AArch64/zero-reg.ll +++ b/llvm/test/CodeGen/AArch64/zero-reg.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-linux-gnu | FileCheck %s @var32 = global i32 0 @var64 = global i64 0 @@ -7,9 +8,9 @@ define void @test_zr() { ; CHECK-LABEL: test_zr: store i32 0, i32* @var32 -; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32] +; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32] store i64 0, i64* @var64 -; CHECK: str xzr, [{{x[0-9]+}}, #:lo12:var64] +; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64] ret void ; CHECK: ret @@ -23,8 +24,7 @@ define void @test_sp(i32 %val) { ; instruction (0b11111 in the Rn field would mean "sp"). %addr = getelementptr i32* null, i64 0 store i32 %val, i32* %addr -; CHECK: mov x[[NULL:[0-9]+]], xzr -; CHECK: str {{w[0-9]+}}, [x[[NULL]]] +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}] ret void ; CHECK: ret |
