diff options
Diffstat (limited to 'llvm/test/CodeGen')
6 files changed, 38 insertions, 53 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir index 2aee3f18bb1..425b44e0cce 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir @@ -6,7 +6,6 @@ name: legal_v4s32_v2s32 alignment: 2 legalized: true regBankSelected: true -tracksRegLiveness: true registers: - { id: 0, class: fpr } - { id: 1, class: fpr } @@ -15,23 +14,21 @@ frameInfo: maxCallFrameSize: 0 body: | bb.0: - liveins: $d0, $d1 ; CHECK-LABEL: name: legal_v4s32_v2s32 - ; CHECK: liveins: $d0, $d1 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub - ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0 + ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub + ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK: $q0 = COPY [[INSvi64lane]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK: RET_ReallyLR %0:fpr(<2 x s32>) = COPY $d0 %1:fpr(<2 x s32>) = COPY $d1 %2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>) $q0 = COPY %2(<4 x s32>) - RET_ReallyLR implicit $q0 + RET_ReallyLR ... --- @@ -39,7 +36,6 @@ name: legal_v8s16_v4s16 alignment: 2 legalized: true regBankSelected: true -tracksRegLiveness: true registers: - { id: 0, class: fpr } - { id: 1, class: fpr } @@ -48,22 +44,20 @@ frameInfo: maxCallFrameSize: 0 body: | bb.0: - liveins: $d0, $d1 ; CHECK-LABEL: name: legal_v8s16_v4s16 - ; CHECK: liveins: $d0, $d1 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub - ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0 + ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub + ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK: $q0 = COPY [[INSvi64lane]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK: RET_ReallyLR %0:fpr(<4 x s16>) = COPY $d0 %1:fpr(<4 x s16>) = COPY $d1 %2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>) $q0 = COPY %2(<8 x s16>) - RET_ReallyLR implicit $q0 + RET_ReallyLR ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir index 90de1f6df2c..bc59d6df2b3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -41,10 +41,9 @@ body: | liveins: $w0 ; CHECK-LABEL: name: anyext_s64_from_s32 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32 - ; CHECK: $x0 = COPY [[INSERT_SUBREG]] + ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 + ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] %0(s32) = COPY $w0 %1(s64) = G_ANYEXT %0 $x0 = COPY %1(s64) @@ -65,8 +64,8 @@ body: | ; CHECK-LABEL: name: anyext_s32_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]] - ; CHECK: $w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]] + ; CHECK: $w0 = COPY [[COPY2]] %2:gpr(s32) = COPY $w0 %0(s8) = G_TRUNC %2 %1(s32) = G_ANYEXT %0 @@ -237,8 +236,8 @@ body: | ; CHECK-LABEL: name: zext_s16_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]] - ; CHECK: $w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]] + ; CHECK: $w0 = COPY [[COPY2]] %2:gpr(s32) = COPY $w0 %0(s8) = G_TRUNC %2 %1(s16) = G_ZEXT %0 @@ -340,9 +339,8 @@ body: | ; CHECK-LABEL: name: sext_s64_from_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32 - ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 + ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31 ; CHECK: $x0 = COPY [[SBFMXri]] %0(s32) = COPY $w0 %1(s64) = G_SEXT %0 @@ -411,8 +409,8 @@ body: | ; CHECK-LABEL: name: sext_s16_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]] - ; CHECK: $w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]] + ; CHECK: $w0 = COPY [[COPY2]] %2:gpr(s32) = COPY $w0 %0(s8) = G_TRUNC %2 %1(s16) = G_SEXT %0 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir index 5e36ffa6fc5..3ff39879820 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir @@ -179,18 +179,16 @@ regBankSelected: true # ALL: registers: # ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } # ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } - { id: 2, class: gpr, preferred-register: '' } -# ALL: %0:gr32 = COPY $edx -# ALL-NEXT: %1:gr16 = COPY %0.sub_16bit -# ALL-NEXT: %3:low32_addr_access_rbp = IMPLICIT_DEF -# ALL-NEXT: %2:low32_addr_access_rbp = INSERT_SUBREG %3, %1, %subreg.sub_16bit -# ALL-NEXT: $eax = COPY %2 -# ALL-NEXT: RET 0, implicit $eax +# ALL %0:gr32 = COPY $edx +# ALL-NEXT %1:gr16 = COPY %0.sub_16bit +# ALL-NEXT %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit +# ALL-NEXT $eax = COPY %2 +# ALL-NEXT RET 0, implicit $eax body: | bb.1 (%ir-block.0): liveins: $eax,$edx @@ -202,3 +200,4 @@ body: | RET 0, implicit $eax ... + diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir index f384433c331..b5caaf0e308 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -186,9 +186,8 @@ body: | ; ALL-LABEL: name: anyext_s64_from_s32 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit - ; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32bit - ; ALL: $rax = COPY [[INSERT_SUBREG]] + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32bit + ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s32) = G_TRUNC %0(s64) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index ce3e7900731..dc077dda880 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -446,16 +446,14 @@ regBankSelected: true # ALL: registers: # ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } # ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } # ALL: %0:gr32 = COPY $edi # ALL-NEXT: %1:gr16 = COPY %0.sub_16bit -# ALL-NEXT: %3:low32_addr_access_rbp = IMPLICIT_DEF -# ALL-NEXT: %2:low32_addr_access_rbp = INSERT_SUBREG %3, %1, %subreg.sub_16bit +# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit # ALL-NEXT: $eax = COPY %2 # ALL-NEXT: RET 0, implicit $eax body: | diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir index d5bccf9a059..1883368a4a1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir @@ -165,9 +165,8 @@ body: | ; CHECK-LABEL: name: zext_i1_to_i64 ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit - ; CHECK: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit + ; CHECK: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags ; CHECK: $rax = COPY [[AND64ri8_]] ; CHECK: RET 0, implicit $rax %1:gpr(s32) = COPY $edi @@ -259,9 +258,8 @@ body: | ; CHECK-LABEL: name: zext_i8_to_i64 ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit - ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit + ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[SUBREG_TO_REG]], 255, implicit-def $eflags ; CHECK: $rax = COPY [[AND64ri32_]] ; CHECK: RET 0, implicit $rax %1:gpr(s32) = COPY $edi @@ -322,9 +320,8 @@ body: | ; CHECK-LABEL: name: zext_i16_to_i64 ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit - ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit + ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[SUBREG_TO_REG]], 65535, implicit-def $eflags ; CHECK: $rax = COPY [[AND64ri32_]] ; CHECK: RET 0, implicit $rax %1:gpr(s32) = COPY $edi |
