diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll | 17 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 27 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm_constraint.ll | 20 |
5 files changed, 99 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll new file mode 100644 index 00000000000..f9e53cbb07a --- /dev/null +++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll @@ -0,0 +1,15 @@ +; +;This is a negative test. The constant value given for the constraint +;is greater than 16 bits. +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'I' + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind + ret i32 0 +} + diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll new file mode 100644 index 00000000000..f5255fe0a3b --- /dev/null +++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll @@ -0,0 +1,17 @@ +; +; Register constraint "r" shouldn't take long long unless +; The target is 64 bit. +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +; r with long long +;CHECK-ERRORS: error: couldn't allocate output register for constraint 'r' + + tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind + ret i32 0 +} + diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll new file mode 100644 index 00000000000..ac84d2a16ec --- /dev/null +++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -0,0 +1,27 @@ +; Positive test for inline register constraints +; +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i32 @main() nounwind { +entry: + +; r with char +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},23 +;CHECK: #NO_APP + tail call i8 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind + +; r with short +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},13 +;CHECK: #NO_APP + tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind + +; r with int +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind + + ret i32 0 +} diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll new file mode 100644 index 00000000000..78706660257 --- /dev/null +++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll @@ -0,0 +1,20 @@ +; +; Register constraint "r" shouldn't take long long unless +; The target is 64 bit. +; +; +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s + + +define i32 @main() nounwind { +entry: + + +; r with long long +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind + ret i32 0 +} + diff --git a/llvm/test/CodeGen/Mips/inlineasm_constraint.ll b/llvm/test/CodeGen/Mips/inlineasm_constraint.ll new file mode 100644 index 00000000000..e2fbaa772ef --- /dev/null +++ b/llvm/test/CodeGen/Mips/inlineasm_constraint.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i32 @main() nounwind { +entry: + +; First I with short +; CHECK: #APP +; CHECK: addi $3,$2,4096 +; CHECK: #NO_APP + tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind + +; Then I with int +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind + + ret i32 0 +} + |
