diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/bit-validate-reg.ll | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll b/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll new file mode 100644 index 00000000000..16d4a5e4484 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Make sure we don't generate zxtb to transfer a predicate register into +; a general purpose register. + +; CHECK: r0 = p0 +; CHECK-NOT: zxtb(p + +target triple = "hexagon" + +; Function Attrs: nounwind +define i32 @fred() local_unnamed_addr #0 { +entry: + %0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef) + ret i32 %0 +} + +declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1 + +attributes #0 = { nounwind "target-cpu"="hexagonv5" } +attributes #1 = { nounwind readnone } |
