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-rw-r--r--llvm/test/CodeGen/XCore/2009-01-08-Crash.ll2
-rw-r--r--llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll2
-rw-r--r--llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll2
-rw-r--r--llvm/test/CodeGen/XCore/atomic.ll18
-rw-r--r--llvm/test/CodeGen/XCore/codemodel.ll18
-rw-r--r--llvm/test/CodeGen/XCore/dwarf_debug.ll2
-rw-r--r--llvm/test/CodeGen/XCore/exception.ll2
-rw-r--r--llvm/test/CodeGen/XCore/indirectbr.ll4
-rw-r--r--llvm/test/CodeGen/XCore/llvm-intrinsics.ll2
-rw-r--r--llvm/test/CodeGen/XCore/load.ll10
-rw-r--r--llvm/test/CodeGen/XCore/private.ll2
-rw-r--r--llvm/test/CodeGen/XCore/scavenging.ll26
-rw-r--r--llvm/test/CodeGen/XCore/trampoline.ll2
-rw-r--r--llvm/test/CodeGen/XCore/unaligned_load.ll6
-rw-r--r--llvm/test/CodeGen/XCore/unaligned_store_combine.ll2
-rw-r--r--llvm/test/CodeGen/XCore/zextfree.ll2
16 files changed, 51 insertions, 51 deletions
diff --git a/llvm/test/CodeGen/XCore/2009-01-08-Crash.ll b/llvm/test/CodeGen/XCore/2009-01-08-Crash.ll
index 6b55e892c89..5eddbc33761 100644
--- a/llvm/test/CodeGen/XCore/2009-01-08-Crash.ll
+++ b/llvm/test/CodeGen/XCore/2009-01-08-Crash.ll
@@ -7,6 +7,6 @@ define i32 @test(i32 %bar) nounwind readnone {
entry:
%bar_addr = alloca i32
%0 = getelementptr i32, i32* %bar_addr, i32 -1
- %1 = load i32* %0, align 4
+ %1 = load i32, i32* %0, align 4
ret i32 %1
}
diff --git a/llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll b/llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
index 396b083f592..693e6f0f136 100644
--- a/llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
+++ b/llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
@@ -16,7 +16,7 @@ bb3.i15.i.i: ; preds = %bb3.i15.i.i, %entry
%tmp137 = sub i32 0, %indvar.i.i.i ; <i32> [#uses=1]
%scevgep13.i.i.i = getelementptr i32, i32* undef, i32 %tmp137 ; <i32*> [#uses=2]
%scevgep1314.i.i.i = bitcast i32* %scevgep13.i.i.i to %struct.dwarf_fde** ; <%struct.dwarf_fde**> [#uses=1]
- %0 = load %struct.dwarf_fde** %scevgep1314.i.i.i, align 4 ; <%struct.dwarf_fde*> [#uses=0]
+ %0 = load %struct.dwarf_fde*, %struct.dwarf_fde** %scevgep1314.i.i.i, align 4 ; <%struct.dwarf_fde*> [#uses=0]
store i32 undef, i32* %scevgep13.i.i.i
%indvar.next.i.i.i = add i32 %indvar.i.i.i, 1 ; <i32> [#uses=1]
br label %bb3.i15.i.i
diff --git a/llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll b/llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
index f8fe0d2136f..92391de8fa3 100644
--- a/llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
+++ b/llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
@@ -5,6 +5,6 @@
define i32 @test_entry() nounwind {
entry:
- %0 = load i32* getelementptr inbounds (%struct.st* @x, i32 0, i32 3), align 2
+ %0 = load i32, i32* getelementptr inbounds (%struct.st* @x, i32 0, i32 3), align 2
ret i32 %0
}
diff --git a/llvm/test/CodeGen/XCore/atomic.ll b/llvm/test/CodeGen/XCore/atomic.ll
index 6ca80cf5d9e..13579dbd819 100644
--- a/llvm/test/CodeGen/XCore/atomic.ll
+++ b/llvm/test/CodeGen/XCore/atomic.ll
@@ -25,27 +25,27 @@ entry:
; CHECK-NEXT: ldaw r[[R1:[0-9]+]], dp[pool]
; CHECK-NEXT: #MEMBARRIER
; CHECK-NEXT: ldc r[[R2:[0-9]+]], 0
- %0 = load atomic i32* bitcast (i64* @pool to i32*) acquire, align 4
+ %0 = load atomic i32, i32* bitcast (i64* @pool to i32*) acquire, align 4
; CHECK-NEXT: ld16s r3, r[[R1]][r[[R2]]]
; CHECK-NEXT: #MEMBARRIER
- %1 = load atomic i16* bitcast (i64* @pool to i16*) acquire, align 2
+ %1 = load atomic i16, i16* bitcast (i64* @pool to i16*) acquire, align 2
; CHECK-NEXT: ld8u r11, r[[R1]][r[[R2]]]
; CHECK-NEXT: #MEMBARRIER
- %2 = load atomic i8* bitcast (i64* @pool to i8*) acquire, align 1
+ %2 = load atomic i8, i8* bitcast (i64* @pool to i8*) acquire, align 1
; CHECK-NEXT: ldw r4, dp[pool]
; CHECK-NEXT: #MEMBARRIER
- %3 = load atomic i32* bitcast (i64* @pool to i32*) seq_cst, align 4
+ %3 = load atomic i32, i32* bitcast (i64* @pool to i32*) seq_cst, align 4
; CHECK-NEXT: ld16s r5, r[[R1]][r[[R2]]]
; CHECK-NEXT: #MEMBARRIER
- %4 = load atomic i16* bitcast (i64* @pool to i16*) seq_cst, align 2
+ %4 = load atomic i16, i16* bitcast (i64* @pool to i16*) seq_cst, align 2
; CHECK-NEXT: ld8u r6, r[[R1]][r[[R2]]]
; CHECK-NEXT: #MEMBARRIER
- %5 = load atomic i8* bitcast (i64* @pool to i8*) seq_cst, align 1
+ %5 = load atomic i8, i8* bitcast (i64* @pool to i8*) seq_cst, align 1
; CHECK-NEXT: #MEMBARRIER
; CHECK-NEXT: stw r[[R0]], dp[pool]
@@ -80,11 +80,11 @@ entry:
; CHECK-NEXT: st16 r[[R0]], r[[R1]][r[[R2]]]
; CHECK-NEXT: ld8u r[[R0]], r[[R1]][r[[R2]]]
; CHECK-NEXT: st8 r[[R0]], r[[R1]][r[[R2]]]
- %6 = load atomic i32* bitcast (i64* @pool to i32*) monotonic, align 4
+ %6 = load atomic i32, i32* bitcast (i64* @pool to i32*) monotonic, align 4
store atomic i32 %6, i32* bitcast (i64* @pool to i32*) monotonic, align 4
- %7 = load atomic i16* bitcast (i64* @pool to i16*) monotonic, align 2
+ %7 = load atomic i16, i16* bitcast (i64* @pool to i16*) monotonic, align 2
store atomic i16 %7, i16* bitcast (i64* @pool to i16*) monotonic, align 2
- %8 = load atomic i8* bitcast (i64* @pool to i8*) monotonic, align 1
+ %8 = load atomic i8, i8* bitcast (i64* @pool to i8*) monotonic, align 1
store atomic i8 %8, i8* bitcast (i64* @pool to i8*) monotonic, align 1
ret void
diff --git a/llvm/test/CodeGen/XCore/codemodel.ll b/llvm/test/CodeGen/XCore/codemodel.ll
index d2091251d30..706c38075ab 100644
--- a/llvm/test/CodeGen/XCore/codemodel.ll
+++ b/llvm/test/CodeGen/XCore/codemodel.ll
@@ -97,21 +97,21 @@ entry:
define i32 @f(i32* %i) {
entry:
%0 = getelementptr inbounds i32, i32* %i, i32 16383
- %1 = load i32* %0
+ %1 = load i32, i32* %0
%2 = getelementptr inbounds i32, i32* %i, i32 16384
- %3 = load i32* %2
+ %3 = load i32, i32* %2
%4 = add nsw i32 %1, %3
- %5 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 0)
+ %5 = load i32, i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 0)
%6 = add nsw i32 %4, %5
- %7 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 1)
+ %7 = load i32, i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 1)
%8 = add nsw i32 %6, %7
- %9 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 98)
+ %9 = load i32, i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 98)
%10 = add nsw i32 %8, %9
- %11 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 99)
+ %11 = load i32, i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 99)
%12 = add nsw i32 %10, %11
- %13 = load i32* getelementptr inbounds ([10 x i32]* @s, i32 0, i32 0)
+ %13 = load i32, i32* getelementptr inbounds ([10 x i32]* @s, i32 0, i32 0)
%14 = add nsw i32 %12, %13
- %15 = load i32* getelementptr inbounds ([10 x i32]* @s, i32 0, i32 9)
+ %15 = load i32, i32* getelementptr inbounds ([10 x i32]* @s, i32 0, i32 9)
%16 = add nsw i32 %14, %15
ret i32 %16
}
@@ -132,7 +132,7 @@ entry:
@NoSize = external global [0 x i32]
define i32 @UnknownSize() nounwind {
entry:
- %0 = load i32* getelementptr inbounds ([0 x i32]* @NoSize, i32 0, i32 10)
+ %0 = load i32, i32* getelementptr inbounds ([0 x i32]* @NoSize, i32 0, i32 10)
ret i32 %0
}
diff --git a/llvm/test/CodeGen/XCore/dwarf_debug.ll b/llvm/test/CodeGen/XCore/dwarf_debug.ll
index 8c9c47de649..783138b11da 100644
--- a/llvm/test/CodeGen/XCore/dwarf_debug.ll
+++ b/llvm/test/CodeGen/XCore/dwarf_debug.ll
@@ -14,7 +14,7 @@ entry:
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !11, metadata !{!"0x102"}), !dbg !12
- %0 = load i32* %a.addr, align 4, !dbg !12
+ %0 = load i32, i32* %a.addr, align 4, !dbg !12
%add = add nsw i32 %0, 1, !dbg !12
ret i32 %add, !dbg !12
}
diff --git a/llvm/test/CodeGen/XCore/exception.ll b/llvm/test/CodeGen/XCore/exception.ll
index dcff0d6be8b..6572dc80098 100644
--- a/llvm/test/CodeGen/XCore/exception.ll
+++ b/llvm/test/CodeGen/XCore/exception.ll
@@ -84,7 +84,7 @@ lpad:
%2 = extractvalue { i8*, i32 } %0, 1
%3 = call i8* @__cxa_begin_catch(i8* %1) nounwind
%4 = bitcast i8* %3 to i32*
- %5 = load i32* %4
+ %5 = load i32, i32* %4
call void @__cxa_end_catch() nounwind
; CHECK: eq r0, r6, r5
diff --git a/llvm/test/CodeGen/XCore/indirectbr.ll b/llvm/test/CodeGen/XCore/indirectbr.ll
index 3565b20eb1c..9723cdcbdf1 100644
--- a/llvm/test/CodeGen/XCore/indirectbr.ll
+++ b/llvm/test/CodeGen/XCore/indirectbr.ll
@@ -6,7 +6,7 @@
define internal i32 @foo(i32 %i) nounwind {
; CHECK-LABEL: foo:
entry:
- %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
+ %0 = load i8*, i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
br i1 %1, label %bb3, label %bb2
@@ -17,7 +17,7 @@ bb2: ; preds = %entry, %bb3
bb3: ; preds = %entry
%2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
- %gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1]
+ %gotovar.4.0.pre = load i8*, i8** %2, align 4 ; <i8*> [#uses=1]
br label %bb2
L5: ; preds = %bb2
diff --git a/llvm/test/CodeGen/XCore/llvm-intrinsics.ll b/llvm/test/CodeGen/XCore/llvm-intrinsics.ll
index b436282615c..539bf199028 100644
--- a/llvm/test/CodeGen/XCore/llvm-intrinsics.ll
+++ b/llvm/test/CodeGen/XCore/llvm-intrinsics.ll
@@ -145,7 +145,7 @@ entry:
; CHECK-NEXT: set sp, r2
; CHECK-NEXT: bau r3
call void (...)* @foo()
- %0 = load i32* @offset
+ %0 = load i32, i32* @offset
call void @llvm.eh.return.i32(i32 %0, i8* @handler)
unreachable
}
diff --git a/llvm/test/CodeGen/XCore/load.ll b/llvm/test/CodeGen/XCore/load.ll
index fc0497814d8..bba7f72301f 100644
--- a/llvm/test/CodeGen/XCore/load.ll
+++ b/llvm/test/CodeGen/XCore/load.ll
@@ -5,7 +5,7 @@ entry:
; CHECK-LABEL: load32:
; CHECK: ldw r0, r0[r1]
%0 = getelementptr i32, i32* %p, i32 %offset
- %1 = load i32* %0, align 4
+ %1 = load i32, i32* %0, align 4
ret i32 %1
}
@@ -14,7 +14,7 @@ entry:
; CHECK-LABEL: load32_imm:
; CHECK: ldw r0, r0[11]
%0 = getelementptr i32, i32* %p, i32 11
- %1 = load i32* %0, align 4
+ %1 = load i32, i32* %0, align 4
ret i32 %1
}
@@ -24,7 +24,7 @@ entry:
; CHECK: ld16s r0, r0[r1]
; CHECK-NOT: sext
%0 = getelementptr i16, i16* %p, i32 %offset
- %1 = load i16* %0, align 2
+ %1 = load i16, i16* %0, align 2
%2 = sext i16 %1 to i32
ret i32 %2
}
@@ -35,7 +35,7 @@ entry:
; CHECK: ld8u r0, r0[r1]
; CHECK-NOT: zext
%0 = getelementptr i8, i8* %p, i32 %offset
- %1 = load i8* %0, align 1
+ %1 = load i8, i8* %0, align 1
%2 = zext i8 %1 to i32
ret i32 %2
}
@@ -45,6 +45,6 @@ define i32 @load_cp() nounwind {
entry:
; CHECK-LABEL: load_cp:
; CHECK: ldw r0, cp[GConst]
- %0 = load i32* @GConst
+ %0 = load i32, i32* @GConst
ret i32 %0
}
diff --git a/llvm/test/CodeGen/XCore/private.ll b/llvm/test/CodeGen/XCore/private.ll
index 474448a5088..a188864a866 100644
--- a/llvm/test/CodeGen/XCore/private.ll
+++ b/llvm/test/CodeGen/XCore/private.ll
@@ -14,7 +14,7 @@ define i32 @bar() {
; CHECK: bl .Lfoo
; CHECK: ldw r0, dp[.Lbaz]
call void @foo()
- %1 = load i32* @baz, align 4
+ %1 = load i32, i32* @baz, align 4
ret i32 %1
}
diff --git a/llvm/test/CodeGen/XCore/scavenging.ll b/llvm/test/CodeGen/XCore/scavenging.ll
index 2756c125aa8..7b6f54ebec2 100644
--- a/llvm/test/CodeGen/XCore/scavenging.ll
+++ b/llvm/test/CodeGen/XCore/scavenging.ll
@@ -17,20 +17,20 @@
define void @f() nounwind {
entry:
%x = alloca [100 x i32], align 4 ; <[100 x i32]*> [#uses=2]
- %0 = load i32* @size, align 4 ; <i32> [#uses=1]
+ %0 = load i32, i32* @size, align 4 ; <i32> [#uses=1]
%1 = alloca i32, i32 %0, align 4 ; <i32*> [#uses=1]
- %2 = load volatile i32* @g0, align 4 ; <i32> [#uses=1]
- %3 = load volatile i32* @g1, align 4 ; <i32> [#uses=1]
- %4 = load volatile i32* @g2, align 4 ; <i32> [#uses=1]
- %5 = load volatile i32* @g3, align 4 ; <i32> [#uses=1]
- %6 = load volatile i32* @g4, align 4 ; <i32> [#uses=1]
- %7 = load volatile i32* @g5, align 4 ; <i32> [#uses=1]
- %8 = load volatile i32* @g6, align 4 ; <i32> [#uses=1]
- %9 = load volatile i32* @g7, align 4 ; <i32> [#uses=1]
- %10 = load volatile i32* @g8, align 4 ; <i32> [#uses=1]
- %11 = load volatile i32* @g9, align 4 ; <i32> [#uses=1]
- %12 = load volatile i32* @g10, align 4 ; <i32> [#uses=1]
- %13 = load volatile i32* @g11, align 4 ; <i32> [#uses=2]
+ %2 = load volatile i32, i32* @g0, align 4 ; <i32> [#uses=1]
+ %3 = load volatile i32, i32* @g1, align 4 ; <i32> [#uses=1]
+ %4 = load volatile i32, i32* @g2, align 4 ; <i32> [#uses=1]
+ %5 = load volatile i32, i32* @g3, align 4 ; <i32> [#uses=1]
+ %6 = load volatile i32, i32* @g4, align 4 ; <i32> [#uses=1]
+ %7 = load volatile i32, i32* @g5, align 4 ; <i32> [#uses=1]
+ %8 = load volatile i32, i32* @g6, align 4 ; <i32> [#uses=1]
+ %9 = load volatile i32, i32* @g7, align 4 ; <i32> [#uses=1]
+ %10 = load volatile i32, i32* @g8, align 4 ; <i32> [#uses=1]
+ %11 = load volatile i32, i32* @g9, align 4 ; <i32> [#uses=1]
+ %12 = load volatile i32, i32* @g10, align 4 ; <i32> [#uses=1]
+ %13 = load volatile i32, i32* @g11, align 4 ; <i32> [#uses=2]
%14 = getelementptr [100 x i32], [100 x i32]* %x, i32 0, i32 50 ; <i32*> [#uses=1]
store i32 %13, i32* %14, align 4
store volatile i32 %13, i32* @g11, align 4
diff --git a/llvm/test/CodeGen/XCore/trampoline.ll b/llvm/test/CodeGen/XCore/trampoline.ll
index 45d4bf4b363..a7280000500 100644
--- a/llvm/test/CodeGen/XCore/trampoline.ll
+++ b/llvm/test/CodeGen/XCore/trampoline.ll
@@ -29,7 +29,7 @@ entry:
; CHECK-NEXT: ldw r0, r11[0]
; CHECK-NEXT: retsp 0
%0 = getelementptr inbounds %struct.FRAME.f, %struct.FRAME.f* %CHAIN.1, i32 0, i32 0
- %1 = load i32* %0, align 4
+ %1 = load i32, i32* %0, align 4
ret i32 %1
}
diff --git a/llvm/test/CodeGen/XCore/unaligned_load.ll b/llvm/test/CodeGen/XCore/unaligned_load.ll
index b8b88275538..4bec151acae 100644
--- a/llvm/test/CodeGen/XCore/unaligned_load.ll
+++ b/llvm/test/CodeGen/XCore/unaligned_load.ll
@@ -5,7 +5,7 @@
; CHECK: bl __misaligned_load
define i32 @align1(i32* %p) nounwind {
entry:
- %0 = load i32* %p, align 1 ; <i32> [#uses=1]
+ %0 = load i32, i32* %p, align 1 ; <i32> [#uses=1]
ret i32 %0
}
@@ -16,7 +16,7 @@ entry:
; CHECK: or
define i32 @align2(i32* %p) nounwind {
entry:
- %0 = load i32* %p, align 2 ; <i32> [#uses=1]
+ %0 = load i32, i32* %p, align 2 ; <i32> [#uses=1]
ret i32 %0
}
@@ -29,6 +29,6 @@ entry:
; CHECK: or
define i32 @align3() nounwind {
entry:
- %0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
+ %0 = load i32, i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
ret i32 %0
}
diff --git a/llvm/test/CodeGen/XCore/unaligned_store_combine.ll b/llvm/test/CodeGen/XCore/unaligned_store_combine.ll
index d1f4e6c15cd..4b29a05984a 100644
--- a/llvm/test/CodeGen/XCore/unaligned_store_combine.ll
+++ b/llvm/test/CodeGen/XCore/unaligned_store_combine.ll
@@ -7,7 +7,7 @@ entry:
; CHECK-LABEL: f:
; CHECK: ldc r2, 8
; CHECK: bl memmove
- %0 = load i64* %src, align 1
+ %0 = load i64, i64* %src, align 1
store i64 %0, i64* %dst, align 1
ret void
}
diff --git a/llvm/test/CodeGen/XCore/zextfree.ll b/llvm/test/CodeGen/XCore/zextfree.ll
index 48dce886532..d1e2b7f8578 100644
--- a/llvm/test/CodeGen/XCore/zextfree.ll
+++ b/llvm/test/CodeGen/XCore/zextfree.ll
@@ -4,7 +4,7 @@
; CHECK-NOT: zext
define void @test(i8* %s1) {
entry:
- %u8 = load i8* %s1, align 1
+ %u8 = load i8, i8* %s1, align 1
%bool = icmp eq i8 %u8, 0
br label %BB1
BB1:
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