diff options
Diffstat (limited to 'llvm/test/CodeGen/X86')
110 files changed, 884 insertions, 884 deletions
diff --git a/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll index b0eb1c5441b..cea4d9d272f 100644 --- a/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll +++ b/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll @@ -2,7 +2,7 @@ ;; This example can't fold the or into an LEA. define i32 @test(float ** %tmp2, i32 %tmp12) nounwind { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK: orl $1, %{{.*}} ; CHECK: ret @@ -18,7 +18,7 @@ define i32 @test(float ** %tmp2, i32 %tmp12) nounwind { ;; This can! define i32 @test2(i32 %a, i32 %b) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK-NOT: ret ; CHECK: leal 3(,%{{.*}},8) ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll index b48ce845f90..cbc1bc47fb1 100644 --- a/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll +++ b/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i1 %X) { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK: movl $1, %eax ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll index e2cd750e2ca..3e1786bef79 100644 --- a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll +++ b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32" target triple = "i686-apple-darwin9" define void @test() { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK: psrlw $8, %xmm0 ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll index 6e9a6298436..d4805b4bb63 100644 --- a/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll +++ b/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 target triple = "i386-apple-darwin8" define void @test() nounwind { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK: 1 $2 3 ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll index 39c213f00ab..7515e80ef43 100644 --- a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll +++ b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll @@ -5,7 +5,7 @@ ; the chains correctly. ; PR10747 -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: pextrd $2, %xmm define <4 x i32> @test(<4 x i32>* %p) { %v = load <4 x i32>* %p diff --git a/llvm/test/CodeGen/X86/3addr-or.ll b/llvm/test/CodeGen/X86/3addr-or.ll index 912bdc21547..76fabbf0f6a 100644 --- a/llvm/test/CodeGen/X86/3addr-or.ll +++ b/llvm/test/CodeGen/X86/3addr-or.ll @@ -3,7 +3,7 @@ define i32 @test1(i32 %x) nounwind readnone ssp { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: leal 3(%rdi), %eax %0 = shl i32 %x, 5 ; <i32> [#uses=1] %1 = or i32 %0, 3 ; <i32> [#uses=1] @@ -11,7 +11,7 @@ entry: } define i64 @test2(i8 %A, i8 %B) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: shrq $4 ; CHECK-NOT: movq ; CHECK-NOT: orq @@ -31,7 +31,7 @@ define i64 @test2(i8 %A, i8 %B) nounwind { define void @test3(i32 %x, i32* %P) nounwind readnone ssp { entry: ; No reason to emit an add here, should be an or. -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: orl $3, %edi %0 = shl i32 %x, 5 %1 = or i32 %0, 3 @@ -45,7 +45,7 @@ entry: %and2 = and i32 %b, 16 %or = or i32 %and2, %and ret i32 %or -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: leal (%rsi,%rdi), %eax } @@ -56,6 +56,6 @@ entry: %or = or i32 %and2, %and store i32 %or, i32* %P, align 4 ret void -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: orl } diff --git a/llvm/test/CodeGen/X86/add-of-carry.ll b/llvm/test/CodeGen/X86/add-of-carry.ll index 4e30f2b05a8..1513fcba774 100644 --- a/llvm/test/CodeGen/X86/add-of-carry.ll +++ b/llvm/test/CodeGen/X86/add-of-carry.ll @@ -3,7 +3,7 @@ define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: cmpl %ecx, %eax ; CHECK-NOT: addl ; CHECK: adcl $0, %eax @@ -15,7 +15,7 @@ entry: } ; Instcombine transforms test1 into test2: -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl ; CHECK-NEXT: addl ; CHECK-NEXT: adcl $0 @@ -37,7 +37,7 @@ entry: %dec = sext i1 %cmp to i32 %dec.res = add nsw i32 %dec, %res ret i32 %dec.res -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmpl ; CHECK: sbbl ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll index 5fe08ed305f..f36577b26a1 100644 --- a/llvm/test/CodeGen/X86/add.ll +++ b/llvm/test/CodeGen/X86/add.ll @@ -39,11 +39,11 @@ normal: overflow: ret i1 false -; X32: test4: +; X32-LABEL: test4: ; X32: addl ; X32-NEXT: jo -; X64: test4: +; X64-LABEL: test4: ; X64: addl %e[[A1:si|dx]], %e[[A0:di|cx]] ; X64-NEXT: jo } @@ -62,11 +62,11 @@ normal: carry: ret i1 false -; X32: test5: +; X32-LABEL: test5: ; X32: addl ; X32-NEXT: jb -; X64: test5: +; X64-LABEL: test5: ; X64: addl %e[[A1]], %e[[A0]] ; X64-NEXT: jb } @@ -81,13 +81,13 @@ define i64 @test6(i64 %A, i32 %B) nounwind { %tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1] ret i64 %tmp5 -; X32: test6: +; X32-LABEL: test6: ; X32: movl 12(%esp), %edx ; X32-NEXT: addl 8(%esp), %edx ; X32-NEXT: movl 4(%esp), %eax ; X32-NEXT: ret -; X64: test6: +; X64-LABEL: test6: ; X64: shlq $32, %r[[A1]] ; X64: leaq (%r[[A1]],%r[[A0]]), %rax ; X64: ret @@ -98,7 +98,7 @@ define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind { ret {i32, i1} %t } -; X64: test7: +; X64-LABEL: test7: ; X64: addl %e[[A1]], %e ; X64-NEXT: setb %dl ; X64: ret @@ -117,7 +117,7 @@ entry: ret {i64, i1} %final1 } -; X64: test8: +; X64-LABEL: test8: ; X64: addq ; X64-NEXT: setb ; X64: ret @@ -127,7 +127,7 @@ define i32 @test9(i32 %x, i32 %y) nounwind readnone { %sub = sext i1 %cmp to i32 %cond = add i32 %sub, %y ret i32 %cond -; X64: test9: +; X64-LABEL: test9: ; X64: cmpl $10 ; X64: sete ; X64: subl @@ -140,11 +140,11 @@ entry: %obit = extractvalue {i32, i1} %t, 1 ret i1 %obit -; X32: test10: +; X32-LABEL: test10: ; X32: incl ; X32-NEXT: seto -; X64: test10: +; X64-LABEL: test10: ; X64: incl ; X64-NEXT: seto } diff --git a/llvm/test/CodeGen/X86/asm-modifier.ll b/llvm/test/CodeGen/X86/asm-modifier.ll index 44f972ec719..47b185a1576 100644 --- a/llvm/test/CodeGen/X86/asm-modifier.ll +++ b/llvm/test/CodeGen/X86/asm-modifier.ll @@ -5,7 +5,7 @@ target triple = "i386-apple-darwin9.6" define i32 @test1() nounwind { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movw %gs:6, %ax %asmtmp.i = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 6) nounwind ; <i16> [#uses=1] %0 = zext i16 %asmtmp.i to i32 ; <i32> [#uses=1] @@ -14,7 +14,7 @@ entry: define zeroext i16 @test2(i32 %address) nounwind { entry: -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movw %gs:(%eax), %ax %asmtmp = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 %address) nounwind ; <i16> [#uses=1] ret i16 %asmtmp @@ -25,7 +25,7 @@ entry: define void @test3() nounwind { entry: -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movl _n, %eax call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @n) nounwind ret void @@ -33,7 +33,7 @@ entry: define void @test4() nounwind { entry: -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movl L_y$non_lazy_ptr, %ecx ; CHECK: movl (%ecx), %eax call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @y) nounwind diff --git a/llvm/test/CodeGen/X86/atom-lea-sp.ll b/llvm/test/CodeGen/X86/atom-lea-sp.ll index 19482e13d8c..1df1974dc49 100644 --- a/llvm/test/CodeGen/X86/atom-lea-sp.ll +++ b/llvm/test/CodeGen/X86/atom-lea-sp.ll @@ -5,13 +5,13 @@ declare void @use_arr(i8*) declare void @many_params(i32, i32, i32, i32, i32, i32) define void @test1() nounwind { -; ATOM: test1: +; ATOM-LABEL: test1: ; ATOM: leal -1052(%esp), %esp ; ATOM-NOT: sub ; ATOM: call ; ATOM: leal 1052(%esp), %esp -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: subl ; CHECK: call ; CHECK-NOT: lea @@ -22,23 +22,23 @@ define void @test1() nounwind { } define void @test2() nounwind { -; ATOM: test2: +; ATOM-LABEL: test2: ; ATOM: leal -28(%esp), %esp ; ATOM: call ; ATOM: leal 28(%esp), %esp -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK-NOT: lea call void @many_params(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) ret void } define void @test3() nounwind { -; ATOM: test3: +; ATOM-LABEL: test3: ; ATOM: leal -8(%esp), %esp ; ATOM: leal 8(%esp), %esp -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK-NOT: lea %x = alloca i32, align 4 %y = alloca i32, align 4 diff --git a/llvm/test/CodeGen/X86/avx-brcond.ll b/llvm/test/CodeGen/X86/avx-brcond.ll index d52ae52e0b9..4313a1594fb 100644 --- a/llvm/test/CodeGen/X86/avx-brcond.ll +++ b/llvm/test/CodeGen/X86/avx-brcond.ll @@ -5,7 +5,7 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64> %p1, <4 x i64> %p2) nounwind define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: vptest ; CHECK-NEXT: jne ; CHECK: ret @@ -29,7 +29,7 @@ return: define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind { entry: -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: vptest ; CHECK-NEXT: jne ; CHECK: ret @@ -53,7 +53,7 @@ return: define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind { entry: -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: vptest ; CHECK-NEXT: jae ; CHECK: ret @@ -77,7 +77,7 @@ return: define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind { entry: -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: vptest ; CHECK-NEXT: jae ; CHECK: ret @@ -101,7 +101,7 @@ return: define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind { entry: -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: vptest ; CHECK-NEXT: jne ; CHECK: ret @@ -125,7 +125,7 @@ return: define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind { entry: -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: vptest ; CHECK-NEXT: je ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/avx-fp2int.ll b/llvm/test/CodeGen/X86/avx-fp2int.ll index a3aadde2bdd..8beaac6a780 100644 --- a/llvm/test/CodeGen/X86/avx-fp2int.ll +++ b/llvm/test/CodeGen/X86/avx-fp2int.ll @@ -2,10 +2,10 @@ ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: vcvttpd2dqy ; CHECK: ret -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: vcvttpd2dqy ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/avx-shuffle.ll b/llvm/test/CodeGen/X86/avx-shuffle.ll index 73faa1fe0d4..655902a8f58 100644 --- a/llvm/test/CodeGen/X86/avx-shuffle.ll +++ b/llvm/test/CodeGen/X86/avx-shuffle.ll @@ -4,14 +4,14 @@ define <4 x float> @test1(<4 x float> %a) nounwind { %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef> ret <4 x float> %b -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: vshufps ; CHECK: vpshufd } ; rdar://10538417 define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: vinsertf128 %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef> %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2> @@ -22,7 +22,7 @@ define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef> ret <4 x i64> %c -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: vperm2f128 ; CHECK: ret } @@ -30,7 +30,7 @@ define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { define <8 x float> @test4(float %a) nounwind { %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 ret <8 x float> %b -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: vinsertf128 } diff --git a/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll b/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll index b0932bdfced..f73174dd2bc 100644 --- a/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll +++ b/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll @@ -5,7 +5,7 @@ @x = common global <8 x float> zeroinitializer, align 32 declare i32 @f(i32, ...) -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: vmovaps %ymm0, (%rsp) define void @test1() nounwind uwtable ssp { entry: diff --git a/llvm/test/CodeGen/X86/avx2-arith.ll b/llvm/test/CodeGen/X86/avx2-arith.ll index 2c0b6685e56..dee4bd3c6bb 100644 --- a/llvm/test/CodeGen/X86/avx2-arith.ll +++ b/llvm/test/CodeGen/X86/avx2-arith.ll @@ -146,4 +146,4 @@ define <8 x i16> @mul_const8(<8 x i16> %x) { define <8 x i32> @mul_const9(<8 x i32> %x) { %y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x i32> %y -}
\ No newline at end of file +} diff --git a/llvm/test/CodeGen/X86/avx2-palignr.ll b/llvm/test/CodeGen/X86/avx2-palignr.ll index 53b9da32ae8..176e02c8382 100644 --- a/llvm/test/CodeGen/X86/avx2-palignr.ll +++ b/llvm/test/CodeGen/X86/avx2-palignr.ll @@ -1,56 +1,56 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s define <8 x i32> @test1(<8 x i32> %A, <8 x i32> %B) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: vpalignr $4 %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12> ret <8 x i32> %C } define <8 x i32> @test2(<8 x i32> %A, <8 x i32> %B) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: vpalignr $4 %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 undef, i32 12> ret <8 x i32> %C } define <8 x i32> @test3(<8 x i32> %A, <8 x i32> %B) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: vpalignr $4 %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12> ret <8 x i32> %C } ; define <8 x i32> @test4(<8 x i32> %A, <8 x i32> %B) nounwind { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: vpalignr $8 %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 10, i32 11, i32 undef, i32 1, i32 14, i32 15, i32 4, i32 5> ret <8 x i32> %C } define <16 x i16> @test5(<16 x i16> %A, <16 x i16> %B) nounwind { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: vpalignr $6 %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 undef, i32 6, i32 7, i32 16, i32 17, i32 18, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26> ret <16 x i16> %C } define <16 x i16> @test6(<16 x i16> %A, <16 x i16> %B) nounwind { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: vpalignr $6 %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26> ret <16 x i16> %C } define <16 x i16> @test7(<16 x i16> %A, <16 x i16> %B) nounwind { -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: vpalignr $6 %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ret <16 x i16> %C } define <32 x i8> @test8(<32 x i8> %A, <32 x i8> %B) nounwind { -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: palignr $5 %C = shufflevector <32 x i8> %A, <32 x i8> %B, <32 x i32> <i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52> ret <32 x i8> %C diff --git a/llvm/test/CodeGen/X86/avx2-vector-shifts.ll b/llvm/test/CodeGen/X86/avx2-vector-shifts.ll index ca18a60b3ca..a978d93fc55 100644 --- a/llvm/test/CodeGen/X86/avx2-vector-shifts.ll +++ b/llvm/test/CodeGen/X86/avx2-vector-shifts.ll @@ -8,7 +8,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_sllw_1: +; CHECK-LABEL: test_sllw_1: ; CHECK: vpsllw $0, %ymm0, %ymm0 ; CHECK: ret @@ -18,7 +18,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_sllw_2: +; CHECK-LABEL: test_sllw_2: ; CHECK: vpaddw %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -28,7 +28,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_sllw_3: +; CHECK-LABEL: test_sllw_3: ; CHECK: vxorps %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -38,7 +38,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_slld_1: +; CHECK-LABEL: test_slld_1: ; CHECK: vpslld $0, %ymm0, %ymm0 ; CHECK: ret @@ -48,7 +48,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_slld_2: +; CHECK-LABEL: test_slld_2: ; CHECK: vpaddd %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -58,7 +58,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_slld_3: +; CHECK-LABEL: test_slld_3: ; CHECK: vxorps %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -68,7 +68,7 @@ entry: ret <4 x i64> %shl } -; CHECK: test_sllq_1: +; CHECK-LABEL: test_sllq_1: ; CHECK: vpsllq $0, %ymm0, %ymm0 ; CHECK: ret @@ -78,7 +78,7 @@ entry: ret <4 x i64> %shl } -; CHECK: test_sllq_2: +; CHECK-LABEL: test_sllq_2: ; CHECK: vpaddq %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -88,7 +88,7 @@ entry: ret <4 x i64> %shl } -; CHECK: test_sllq_3: +; CHECK-LABEL: test_sllq_3: ; CHECK: vxorps %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -100,7 +100,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_sraw_1: +; CHECK-LABEL: test_sraw_1: ; CHECK: vpsraw $0, %ymm0, %ymm0 ; CHECK: ret @@ -110,7 +110,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_sraw_2: +; CHECK-LABEL: test_sraw_2: ; CHECK: vpsraw $1, %ymm0, %ymm0 ; CHECK: ret @@ -120,7 +120,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_sraw_3: +; CHECK-LABEL: test_sraw_3: ; CHECK: vpsraw $16, %ymm0, %ymm0 ; CHECK: ret @@ -130,7 +130,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_srad_1: +; CHECK-LABEL: test_srad_1: ; CHECK: vpsrad $0, %ymm0, %ymm0 ; CHECK: ret @@ -140,7 +140,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_srad_2: +; CHECK-LABEL: test_srad_2: ; CHECK: vpsrad $1, %ymm0, %ymm0 ; CHECK: ret @@ -150,7 +150,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_srad_3: +; CHECK-LABEL: test_srad_3: ; CHECK: vpsrad $32, %ymm0, %ymm0 ; CHECK: ret @@ -162,7 +162,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_srlw_1: +; CHECK-LABEL: test_srlw_1: ; CHECK: vpsrlw $0, %ymm0, %ymm0 ; CHECK: ret @@ -172,7 +172,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_srlw_2: +; CHECK-LABEL: test_srlw_2: ; CHECK: vpsrlw $1, %ymm0, %ymm0 ; CHECK: ret @@ -182,7 +182,7 @@ entry: ret <16 x i16> %shl } -; CHECK: test_srlw_3: +; CHECK-LABEL: test_srlw_3: ; CHECK: vxorps %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -192,7 +192,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_srld_1: +; CHECK-LABEL: test_srld_1: ; CHECK: vpsrld $0, %ymm0, %ymm0 ; CHECK: ret @@ -202,7 +202,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_srld_2: +; CHECK-LABEL: test_srld_2: ; CHECK: vpsrld $1, %ymm0, %ymm0 ; CHECK: ret @@ -212,7 +212,7 @@ entry: ret <8 x i32> %shl } -; CHECK: test_srld_3: +; CHECK-LABEL: test_srld_3: ; CHECK: vxorps %ymm0, %ymm0, %ymm0 ; CHECK: ret @@ -222,7 +222,7 @@ entry: ret <4 x i64> %shl } -; CHECK: test_srlq_1: +; CHECK-LABEL: test_srlq_1: ; CHECK: vpsrlq $0, %ymm0, %ymm0 ; CHECK: ret @@ -232,7 +232,7 @@ entry: ret <4 x i64> %shl } -; CHECK: test_srlq_2: +; CHECK-LABEL: test_srlq_2: ; CHECK: vpsrlq $1, %ymm0, %ymm0 ; CHECK: ret @@ -242,6 +242,6 @@ entry: ret <4 x i64> %shl } -; CHECK: test_srlq_3: +; CHECK-LABEL: test_srlq_3: ; CHECK: vxorps %ymm0, %ymm0, %ymm0 ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll index 139f8b029b2..d3e05d6fbed 100644 --- a/llvm/test/CodeGen/X86/block-placement.ll +++ b/llvm/test/CodeGen/X86/block-placement.ll @@ -5,7 +5,7 @@ declare void @error(i32 %i, i32 %a, i32 %b) define i32 @test_ifchains(i32 %i, i32* %a, i32 %b) { ; Test a chain of ifs, where the block guarded by the if is error handling code ; that is not expected to run. -; CHECK: test_ifchains: +; CHECK-LABEL: test_ifchains: ; CHECK: %entry ; CHECK-NOT: .align ; CHECK: %else1 @@ -79,7 +79,7 @@ exit: define i32 @test_loop_cold_blocks(i32 %i, i32* %a) { ; Check that we sink cold loop blocks after the hot loop body. -; CHECK: test_loop_cold_blocks: +; CHECK-LABEL: test_loop_cold_blocks: ; CHECK: %entry ; CHECK-NOT: .align ; CHECK: %unlikely1 @@ -128,7 +128,7 @@ exit: define i32 @test_loop_early_exits(i32 %i, i32* %a) { ; Check that we sink early exit blocks out of loop bodies. -; CHECK: test_loop_early_exits: +; CHECK-LABEL: test_loop_early_exits: ; CHECK: %entry ; CHECK: %body1 ; CHECK: %body2 @@ -180,7 +180,7 @@ exit: define i32 @test_loop_rotate(i32 %i, i32* %a) { ; Check that we rotate conditional exits from the loop to the bottom of the ; loop, eliminating unconditional branches to the top. -; CHECK: test_loop_rotate: +; CHECK-LABEL: test_loop_rotate: ; CHECK: %entry ; CHECK: %body1 ; CHECK: %body0 @@ -210,7 +210,7 @@ exit: define i32 @test_no_loop_rotate(i32 %i, i32* %a) { ; Check that we don't try to rotate a loop which is already laid out with ; fallthrough opportunities into the top and out of the bottom. -; CHECK: test_no_loop_rotate: +; CHECK-LABEL: test_no_loop_rotate: ; CHECK: %entry ; CHECK: %body0 ; CHECK: %body1 @@ -278,7 +278,7 @@ exit: define i32 @test_loop_align(i32 %i, i32* %a) { ; Check that we provide basic loop body alignment with the block placement ; pass. -; CHECK: test_loop_align: +; CHECK-LABEL: test_loop_align: ; CHECK: %entry ; CHECK: .align [[ALIGN:[0-9]+]], ; CHECK-NEXT: %body @@ -303,7 +303,7 @@ exit: define i32 @test_nested_loop_align(i32 %i, i32* %a, i32* %b) { ; Check that we provide nested loop body alignment. -; CHECK: test_nested_loop_align: +; CHECK-LABEL: test_nested_loop_align: ; CHECK: %entry ; CHECK: .align [[ALIGN]], ; CHECK-NEXT: %loop.body.1 @@ -1096,7 +1096,7 @@ define i32 @test_cold_calls(i32* %a) { ; Test that edges to blocks post-dominated by cold calls are ; marked as not expected to be taken. They should be laid out ; at the bottom. -; CHECK: test_cold_calls: +; CHECK-LABEL: test_cold_calls: ; CHECK: %entry ; CHECK: %else ; CHECK: %exit diff --git a/llvm/test/CodeGen/X86/brcond.ll b/llvm/test/CodeGen/X86/brcond.ll index bc4032b13cc..3ebe1a1d235 100644 --- a/llvm/test/CodeGen/X86/brcond.ll +++ b/llvm/test/CodeGen/X86/brcond.ll @@ -4,7 +4,7 @@ define i32 @test1(i32 %a, i32 %b) nounwind ssp { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: xorb ; CHECK-NOT: andb ; CHECK-NOT: shrb @@ -44,7 +44,7 @@ bb1: ; preds = %entry return: ; preds = %entry ret i32 192 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax ; CHECK-NEXT: jne LBB1_2 @@ -63,7 +63,7 @@ bb1: ; preds = %entry return: ; preds = %entry ret i32 192 -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax ; CHECK-NEXT: je LBB2_2 @@ -113,7 +113,7 @@ declare i32 @llvm.x86.sse41.ptestc(<4 x float> %p1, <4 x float> %p2) nounwind define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind { entry: -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: ptest ; CHECK-NEXT: jne ; CHECK: ret @@ -137,7 +137,7 @@ return: define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind { entry: -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: ptest ; CHECK-NEXT: jne ; CHECK: ret @@ -161,7 +161,7 @@ return: define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind { entry: -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: ptest ; CHECK-NEXT: jae ; CHECK: ret @@ -185,7 +185,7 @@ return: define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind { entry: -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: ptest ; CHECK-NEXT: jae ; CHECK: ret @@ -209,7 +209,7 @@ return: define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind { entry: -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: ptest ; CHECK-NEXT: jne ; CHECK: ret @@ -233,7 +233,7 @@ return: define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind { entry: -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: ptest ; CHECK-NEXT: je ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/btq.ll b/llvm/test/CodeGen/X86/btq.ll index 9c137a7239b..add65765e38 100644 --- a/llvm/test/CodeGen/X86/btq.ll +++ b/llvm/test/CodeGen/X86/btq.ll @@ -7,7 +7,7 @@ define void @test1(i64 %foo) nounwind { %tobool = icmp eq i64 %and, 0 br i1 %tobool, label %if.end, label %if.then -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: btq $32 if.then: @@ -23,7 +23,7 @@ define void @test2(i64 %foo) nounwind { %tobool = icmp eq i64 %and, 0 br i1 %tobool, label %if.end, label %if.then -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: testl $-2147483648 if.then: diff --git a/llvm/test/CodeGen/X86/cmov-fp.ll b/llvm/test/CodeGen/X86/cmov-fp.ll index ca91f9ea2c2..768af943eb4 100644 --- a/llvm/test/CodeGen/X86/cmov-fp.ll +++ b/llvm/test/CodeGen/X86/cmov-fp.ll @@ -9,16 +9,16 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test1: +; SSE-LABEL: test1: ; SSE: movsd -; NOSSE2: test1: +; NOSSE2-LABEL: test1: ; NOSSE2: fcmovnbe -; NOSSE1: test1: +; NOSSE1-LABEL: test1: ; NOSSE1: fcmovnbe -; NOCMOV: test1: +; NOCMOV-LABEL: test1: ; NOCMOV: fstp } @@ -28,16 +28,16 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test2: +; SSE-LABEL: test2: ; SSE: movsd -; NOSSE2: test2: +; NOSSE2-LABEL: test2: ; NOSSE2: fcmovnb -; NOSSE1: test2: +; NOSSE1-LABEL: test2: ; NOSSE1: fcmovnb -; NOCMOV: test2: +; NOCMOV-LABEL: test2: ; NOCMOV: fstp } @@ -46,16 +46,16 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test3: +; SSE-LABEL: test3: ; SSE: movsd -; NOSSE2: test3: +; NOSSE2-LABEL: test3: ; NOSSE2: fcmovb -; NOSSE1: test3: +; NOSSE1-LABEL: test3: ; NOSSE1: fcmovb -; NOCMOV: test3: +; NOCMOV-LABEL: test3: ; NOCMOV: fstp } @@ -64,16 +64,16 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test4: +; SSE-LABEL: test4: ; SSE: movsd -; NOSSE2: test4: +; NOSSE2-LABEL: test4: ; NOSSE2: fcmovbe -; NOSSE1: test4: +; NOSSE1-LABEL: test4: ; NOSSE1: fcmovbe -; NOCMOV: test4: +; NOCMOV-LABEL: test4: ; NOCMOV: fstp } @@ -82,16 +82,16 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test5: +; SSE-LABEL: test5: ; SSE: movsd -; NOSSE2: test5: +; NOSSE2-LABEL: test5: ; NOSSE2: fstp -; NOSSE1: test5: +; NOSSE1-LABEL: test5: ; NOSSE1: fstp -; NOCMOV: test5: +; NOCMOV-LABEL: test5: ; NOCMOV: fstp } @@ -100,16 +100,16 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test6: +; SSE-LABEL: test6: ; SSE: movsd -; NOSSE2: test6: +; NOSSE2-LABEL: test6: ; NOSSE2: fstp -; NOSSE1: test6: +; NOSSE1-LABEL: test6: ; NOSSE1: fstp -; NOCMOV: test6: +; NOCMOV-LABEL: test6: ; NOCMOV: fstp } @@ -118,16 +118,16 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test7: +; SSE-LABEL: test7: ; SSE: movsd -; NOSSE2: test7: +; NOSSE2-LABEL: test7: ; NOSSE2: fstp -; NOSSE1: test7: +; NOSSE1-LABEL: test7: ; NOSSE1: fstp -; NOCMOV: test7: +; NOCMOV-LABEL: test7: ; NOCMOV: fstp } @@ -136,16 +136,16 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind { %sel = select i1 %cmp, double 99.0, double %x ret double %sel -; SSE: test8: +; SSE-LABEL: test8: ; SSE: movsd -; NOSSE2: test8: +; NOSSE2-LABEL: test8: ; NOSSE2: fstp -; NOSSE1: test8: +; NOSSE1-LABEL: test8: ; NOSSE1: fstp -; NOCMOV: test8: +; NOCMOV-LABEL: test8: ; NOCMOV: fstp } @@ -154,16 +154,16 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test9: +; SSE-LABEL: test9: ; SSE: movss -; NOSSE2: test9: +; NOSSE2-LABEL: test9: ; NOSSE2: movss -; NOSSE1: test9: +; NOSSE1-LABEL: test9: ; NOSSE1: fcmovnbe -; NOCMOV: test9: +; NOCMOV-LABEL: test9: ; NOCMOV: fstp } @@ -172,16 +172,16 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test10: +; SSE-LABEL: test10: ; SSE: movss -; NOSSE2: test10: +; NOSSE2-LABEL: test10: ; NOSSE2: movss -; NOSSE1: test10: +; NOSSE1-LABEL: test10: ; NOSSE1: fcmovnb -; NOCMOV: test10: +; NOCMOV-LABEL: test10: ; NOCMOV: fstp } @@ -190,16 +190,16 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test11: +; SSE-LABEL: test11: ; SSE: movss -; NOSSE2: test11: +; NOSSE2-LABEL: test11: ; NOSSE2: movss -; NOSSE1: test11: +; NOSSE1-LABEL: test11: ; NOSSE1: fcmovb -; NOCMOV: test11: +; NOCMOV-LABEL: test11: ; NOCMOV: fstp } @@ -208,16 +208,16 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test12: +; SSE-LABEL: test12: ; SSE: movss -; NOSSE2: test12: +; NOSSE2-LABEL: test12: ; NOSSE2: movss -; NOSSE1: test12: +; NOSSE1-LABEL: test12: ; NOSSE1: fcmovbe -; NOCMOV: test12: +; NOCMOV-LABEL: test12: ; NOCMOV: fstp } @@ -226,16 +226,16 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test13: +; SSE-LABEL: test13: ; SSE: movss -; NOSSE2: test13: +; NOSSE2-LABEL: test13: ; NOSSE2: movss -; NOSSE1: test13: +; NOSSE1-LABEL: test13: ; NOSSE1: fstp -; NOCMOV: test13: +; NOCMOV-LABEL: test13: ; NOCMOV: fstp } @@ -244,16 +244,16 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test14: +; SSE-LABEL: test14: ; SSE: movss -; NOSSE2: test14: +; NOSSE2-LABEL: test14: ; NOSSE2: movss -; NOSSE1: test14: +; NOSSE1-LABEL: test14: ; NOSSE1: fstp -; NOCMOV: test14: +; NOCMOV-LABEL: test14: ; NOCMOV: fstp } @@ -262,16 +262,16 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test15: +; SSE-LABEL: test15: ; SSE: movss -; NOSSE2: test15: +; NOSSE2-LABEL: test15: ; NOSSE2: movss -; NOSSE1: test15: +; NOSSE1-LABEL: test15: ; NOSSE1: fstp -; NOCMOV: test15: +; NOCMOV-LABEL: test15: ; NOCMOV: fstp } @@ -280,16 +280,16 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind { %sel = select i1 %cmp, float 99.0, float %x ret float %sel -; SSE: test16: +; SSE-LABEL: test16: ; SSE: movss -; NOSSE2: test16: +; NOSSE2-LABEL: test16: ; NOSSE2: movss -; NOSSE1: test16: +; NOSSE1-LABEL: test16: ; NOSSE1: fstp -; NOCMOV: test16: +; NOCMOV-LABEL: test16: ; NOCMOV: fstp } @@ -298,16 +298,16 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test17: +; SSE-LABEL: test17: ; SSE: fcmovnbe -; NOSSE2: test17: +; NOSSE2-LABEL: test17: ; NOSSE2: fcmovnbe -; NOSSE1: test17: +; NOSSE1-LABEL: test17: ; NOSSE1: fcmovnbe -; NOCMOV: test17: +; NOCMOV-LABEL: test17: ; NOCMOV: fstp } @@ -316,16 +316,16 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test18: +; SSE-LABEL: test18: ; SSE: fcmovnb -; NOSSE2: test18: +; NOSSE2-LABEL: test18: ; NOSSE2: fcmovnb -; NOSSE1: test18: +; NOSSE1-LABEL: test18: ; NOSSE1: fcmovnb -; NOCMOV: test18: +; NOCMOV-LABEL: test18: ; NOCMOV: fstp } @@ -334,16 +334,16 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test19: +; SSE-LABEL: test19: ; SSE: fcmovb -; NOSSE2: test19: +; NOSSE2-LABEL: test19: ; NOSSE2: fcmovb -; NOSSE1: test19: +; NOSSE1-LABEL: test19: ; NOSSE1: fcmovb -; NOCMOV: test19: +; NOCMOV-LABEL: test19: ; NOCMOV: fstp } @@ -352,16 +352,16 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test20: +; SSE-LABEL: test20: ; SSE: fcmovbe -; NOSSE2: test20: +; NOSSE2-LABEL: test20: ; NOSSE2: fcmovbe -; NOSSE1: test20: +; NOSSE1-LABEL: test20: ; NOSSE1: fcmovbe -; NOCMOV: test20: +; NOCMOV-LABEL: test20: ; NOCMOV: fstp } @@ -371,19 +371,19 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind { ret x86_fp80 %sel ; We don't emit a branch for fp80, why? -; SSE: test21: +; SSE-LABEL: test21: ; SSE: testb ; SSE: fcmovne -; NOSSE2: test21: +; NOSSE2-LABEL: test21: ; NOSSE2: testb ; NOSSE2: fcmovne -; NOSSE1: test21: +; NOSSE1-LABEL: test21: ; NOSSE1: testb ; NOSSE1: fcmovne -; NOCMOV: test21: +; NOCMOV-LABEL: test21: ; NOCMOV: fstp } @@ -392,19 +392,19 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test22: +; SSE-LABEL: test22: ; SSE: testb ; SSE: fcmovne -; NOSSE2: test22: +; NOSSE2-LABEL: test22: ; NOSSE2: testb ; NOSSE2: fcmovne -; NOSSE1: test22: +; NOSSE1-LABEL: test22: ; NOSSE1: testb ; NOSSE1: fcmovne -; NOCMOV: test22: +; NOCMOV-LABEL: test22: ; NOCMOV: fstp } @@ -413,19 +413,19 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test23: +; SSE-LABEL: test23: ; SSE: testb ; SSE: fcmovne -; NOSSE2: test23: +; NOSSE2-LABEL: test23: ; NOSSE2: testb ; NOSSE2: fcmovne -; NOSSE1: test23: +; NOSSE1-LABEL: test23: ; NOSSE1: testb ; NOSSE1: fcmovne -; NOCMOV: test23: +; NOCMOV-LABEL: test23: ; NOCMOV: fstp } @@ -434,18 +434,18 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind { %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x ret x86_fp80 %sel -; SSE: test24: +; SSE-LABEL: test24: ; SSE: testb ; SSE: fcmovne -; NOSSE2: test24: +; NOSSE2-LABEL: test24: ; NOSSE2: testb ; NOSSE2: fcmovne -; NOSSE1: test24: +; NOSSE1-LABEL: test24: ; NOSSE1: testb ; NOSSE1: fcmovne -; NOCMOV: test24: +; NOCMOV-LABEL: test24: ; NOCMOV: fstp } diff --git a/llvm/test/CodeGen/X86/cmov-into-branch.ll b/llvm/test/CodeGen/X86/cmov-into-branch.ll index 780746ab1ae..cad8dd307b3 100644 --- a/llvm/test/CodeGen/X86/cmov-into-branch.ll +++ b/llvm/test/CodeGen/X86/cmov-into-branch.ll @@ -6,7 +6,7 @@ define i32 @test1(double %a, double* nocapture %b, i32 %x, i32 %y) { %cmp = fcmp olt double %load, %a %cond = select i1 %cmp, i32 %x, i32 %y ret i32 %cond -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: ucomisd ; CHECK-NOT: cmov ; CHECK: j @@ -18,7 +18,7 @@ define i32 @test2(double %a, double %b, i32 %x, i32 %y) { %cmp = fcmp ogt double %a, %b %cond = select i1 %cmp, i32 %x, i32 %y ret i32 %cond -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: ucomisd ; CHECK: cmov } @@ -29,7 +29,7 @@ define i32 @test3(i32 %a, i32* nocapture %b, i32 %x) { %cmp = icmp ult i32 %load, %a %cond = select i1 %cmp, i32 %a, i32 %x ret i32 %cond -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmpl ; CHECK-NOT: cmov ; CHECK: j @@ -43,7 +43,7 @@ define i32 @test4(i32 %a, i32* nocapture %b, i32 %x, i32 %y) { %cond = select i1 %cmp, i32 %x, i32 %y %add = add i32 %cond, %load ret i32 %add -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: cmpl ; CHECK: cmov } @@ -56,7 +56,7 @@ define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) { %cond = select i1 %cmp1, i32 %a, i32 %y %cond5 = select i1 %cmp, i32 %cond, i32 %x ret i32 %cond5 -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: cmpl ; CHECK: cmov ; CHECK: cmov diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll index ed25c82fdda..92c0445d172 100644 --- a/llvm/test/CodeGen/X86/cmov.ll +++ b/llvm/test/CodeGen/X86/cmov.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movl $12, %eax ; CHECK-NEXT: btl ; CHECK-NEXT: cmovael (%rcx), %eax @@ -18,7 +18,7 @@ entry: } define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone { entry: -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl $12, %eax ; CHECK-NEXT: btl ; CHECK-NEXT: cmovbl (%rcx), %eax @@ -40,7 +40,7 @@ entry: declare void @bar(i64) nounwind define void @test3(i64 %a, i64 %b, i1 %p) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmovnel %edi, %esi ; CHECK-NEXT: movl %esi, %edi @@ -87,7 +87,7 @@ bb.i.i.i: ; preds = %entry %4 = load volatile i8* @g_100, align 1 ; <i8> [#uses=0] br label %func_4.exit.i -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: g_100 ; CHECK: testb ; CHECK-NOT: xor @@ -119,7 +119,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind ; rdar://6668608 define i32 @test5(i32* nocapture %P) nounwind readonly { entry: -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: setg %al ; CHECK: movzbl %al, %eax ; CHECK: orl $-2, %eax @@ -133,7 +133,7 @@ entry: define i32 @test6(i32* nocapture %P) nounwind readonly { entry: -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: setl %al ; CHECK: movzbl %al, %eax ; CHECK: leal 4(%rax,%rax,8), %eax @@ -148,7 +148,7 @@ entry: ; Don't try to use a 16-bit conditional move to do an 8-bit select, ; because it isn't worth it. Just use a branch instead. define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind { -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: testb $1, %dil ; CHECK-NEXT: jne LBB diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index 5f5ba21800b..551d9bc6074 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -10,7 +10,7 @@ cond_true: ; preds = %0 ReturnBlock: ; preds = %0 ret i32 0 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: cmpl $0, (%rsi) } @@ -25,7 +25,7 @@ cond_true: ; preds = %0 ReturnBlock: ; preds = %0 ret i32 0 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl (%rsi), %eax ; CHECK: shll $3, %eax ; CHECK: testl %eax, %eax @@ -35,7 +35,7 @@ define i64 @test3(i64 %x) nounwind { %t = icmp eq i64 %x, 0 %r = zext i1 %t to i64 ret i64 %r -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: testq %rdi, %rdi ; CHECK: sete %al ; CHECK: movzbl %al, %eax @@ -46,7 +46,7 @@ define i64 @test4(i64 %x) nounwind { %t = icmp slt i64 %x, 1 %r = zext i1 %t to i64 ret i64 %r -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: testq %rdi, %rdi ; CHECK: setle %al ; CHECK: movzbl %al, %eax @@ -67,7 +67,7 @@ define i32 @test5(double %A) nounwind { bb12:; preds = %entry ret i32 32 -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: ucomisd LCPI4_0(%rip), %xmm0 ; CHECK: ucomisd LCPI4_1(%rip), %xmm0 } @@ -85,7 +85,7 @@ T: F: ret i32 0 -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: cmpq $0, -8(%rsp) ; CHECK: encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] } @@ -93,7 +93,7 @@ F: ; rdar://11866926 define i32 @test7(i64 %res) nounwind { entry: -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK-NOT: movabsq ; CHECK: shrq $32, %rdi ; CHECK: sete @@ -104,7 +104,7 @@ entry: define i32 @test8(i64 %res) nounwind { entry: -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK-NOT: movabsq ; CHECK: shrq $32, %rdi ; CHECK: cmpq $3, %rdi @@ -115,7 +115,7 @@ entry: define i32 @test9(i64 %res) nounwind { entry: -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK-NOT: movabsq ; CHECK: shrq $33, %rdi ; CHECK: sete @@ -126,7 +126,7 @@ entry: define i32 @test10(i64 %res) nounwind { entry: -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK-NOT: movabsq ; CHECK: shrq $32, %rdi ; CHECK: setne @@ -138,7 +138,7 @@ entry: ; rdar://9758774 define i32 @test11(i64 %l) nounwind { entry: -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK-NOT: movabsq ; CHECK-NOT: andq ; CHECK: shrq $47, %rdi @@ -150,7 +150,7 @@ entry: } define i32 @test12() uwtable ssp { -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: testb %1 = call zeroext i1 @test12b() br i1 %1, label %2, label %3 diff --git a/llvm/test/CodeGen/X86/conditional-indecrement.ll b/llvm/test/CodeGen/X86/conditional-indecrement.ll index a3a0c39905a..c3e71180bb1 100644 --- a/llvm/test/CodeGen/X86/conditional-indecrement.ll +++ b/llvm/test/CodeGen/X86/conditional-indecrement.ll @@ -5,7 +5,7 @@ define i32 @test1(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %not.cmp to i32 %retval.0 = add i32 %inc, %b ret i32 %retval.0 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: cmpl $1 ; CHECK: sbbl $-1 ; CHECK: ret @@ -16,7 +16,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %cmp to i32 %retval.0 = add i32 %inc, %b ret i32 %retval.0 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: cmpl $1 ; CHECK: adcl $0 ; CHECK: ret @@ -27,7 +27,7 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %cmp to i32 %retval.0 = add i32 %inc, %b ret i32 %retval.0 -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmpl $1 ; CHECK: adcl $0 ; CHECK: ret @@ -38,7 +38,7 @@ define i32 @test4(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %not.cmp to i32 %retval.0 = add i32 %inc, %b ret i32 %retval.0 -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: cmpl $1 ; CHECK: sbbl $-1 ; CHECK: ret @@ -49,7 +49,7 @@ define i32 @test5(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %not.cmp to i32 %retval.0 = sub i32 %b, %inc ret i32 %retval.0 -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: cmpl $1 ; CHECK: adcl $-1 ; CHECK: ret @@ -60,7 +60,7 @@ define i32 @test6(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %cmp to i32 %retval.0 = sub i32 %b, %inc ret i32 %retval.0 -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: cmpl $1 ; CHECK: sbbl $0 ; CHECK: ret @@ -71,7 +71,7 @@ define i32 @test7(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %cmp to i32 %retval.0 = sub i32 %b, %inc ret i32 %retval.0 -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: cmpl $1 ; CHECK: sbbl $0 ; CHECK: ret @@ -82,7 +82,7 @@ define i32 @test8(i32 %a, i32 %b) nounwind readnone { %inc = zext i1 %not.cmp to i32 %retval.0 = sub i32 %b, %inc ret i32 %retval.0 -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: cmpl $1 ; CHECK: adcl $-1 ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/critical-edge-split-2.ll b/llvm/test/CodeGen/X86/critical-edge-split-2.ll index 70301cd9bcc..44205d6829d 100644 --- a/llvm/test/CodeGen/X86/critical-edge-split-2.ll +++ b/llvm/test/CodeGen/X86/critical-edge-split-2.ll @@ -22,7 +22,7 @@ cond.end.i: ; preds = %entry ret i16 %call1 } -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: testb %dil, %dil ; CHECK: jne LBB0_2 ; CHECK: divl diff --git a/llvm/test/CodeGen/X86/ctpop-combine.ll b/llvm/test/CodeGen/X86/ctpop-combine.ll index 0a3dfca228c..786f7f9b1cc 100644 --- a/llvm/test/CodeGen/X86/ctpop-combine.ll +++ b/llvm/test/CodeGen/X86/ctpop-combine.ll @@ -8,7 +8,7 @@ define i32 @test1(i64 %x) nounwind readnone { %cmp = icmp ugt i32 %cast, 1 %conv = zext i1 %cmp to i32 ret i32 %conv -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: leaq -1([[A0:%rdi|%rcx]]) ; CHECK-NEXT: testq ; CHECK-NEXT: setne @@ -21,7 +21,7 @@ define i32 @test2(i64 %x) nounwind readnone { %cmp = icmp ult i64 %count, 2 %conv = zext i1 %cmp to i32 ret i32 %conv -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: leaq -1([[A0]]) ; CHECK-NEXT: testq ; CHECK-NEXT: sete @@ -34,7 +34,7 @@ define i32 @test3(i64 %x) nounwind readnone { %cmp = icmp ult i6 %cast, 2 %conv = zext i1 %cmp to i32 ret i32 %conv -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmpb $2 ; CHECK: ret } diff --git a/llvm/test/CodeGen/X86/dag-rauw-cse.ll b/llvm/test/CodeGen/X86/dag-rauw-cse.ll index eca8c8641a2..12a2e626687 100644 --- a/llvm/test/CodeGen/X86/dag-rauw-cse.ll +++ b/llvm/test/CodeGen/X86/dag-rauw-cse.ll @@ -2,7 +2,7 @@ ; PR3018 define i32 @test(i32 %A) nounwind { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK: orl $1 ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/dagcombine-buildvector.ll b/llvm/test/CodeGen/X86/dagcombine-buildvector.ll index dae91d5ccdd..cf631c353fc 100644 --- a/llvm/test/CodeGen/X86/dagcombine-buildvector.ll +++ b/llvm/test/CodeGen/X86/dagcombine-buildvector.ll @@ -3,7 +3,7 @@ ; Shows a dag combine bug that will generate an illegal build vector ; with v2i64 build_vector i32, i32. -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: unpcklpd ; CHECK: movapd define void @test(<2 x double>* %dst, <4 x double> %src) nounwind { @@ -13,7 +13,7 @@ entry: ret void } -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movdqa define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind { entry: diff --git a/llvm/test/CodeGen/X86/dbg-value-terminator.ll b/llvm/test/CodeGen/X86/dbg-value-terminator.ll index e7c12507d80..e8246ad69c1 100644 --- a/llvm/test/CodeGen/X86/dbg-value-terminator.ll +++ b/llvm/test/CodeGen/X86/dbg-value-terminator.ll @@ -5,7 +5,7 @@ ; verify-machineinstrs should ensure that DEBUG_VALUEs go before the ; terminator. ; -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: ##DEBUG_VALUE: i %a = type { i32, i32 } diff --git a/llvm/test/CodeGen/X86/divide-by-constant.ll b/llvm/test/CodeGen/X86/divide-by-constant.ll index 9669d97cb7f..98ae1d51db2 100644 --- a/llvm/test/CodeGen/X86/divide-by-constant.ll +++ b/llvm/test/CodeGen/X86/divide-by-constant.ll @@ -6,7 +6,7 @@ define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: imull $63551, %eax, %eax ; CHECK-NEXT: shrl $21, %eax ; CHECK-NEXT: ret @@ -17,7 +17,7 @@ entry: %div = udiv i16 %c, 3 ret i16 %div -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: imull $43691, %eax, %eax ; CHECK-NEXT: shrl $17, %eax ; CHECK-NEXT: ret @@ -28,7 +28,7 @@ entry: %div = udiv i8 %c, 3 ret i8 %div -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movzbl 8(%esp), %eax ; CHECK-NEXT: imull $171, %eax, %eax ; CHECK-NEXT: shrl $9, %eax @@ -39,14 +39,14 @@ define signext i16 @test4(i16 signext %x) nounwind { entry: %div = sdiv i16 %x, 33 ; <i32> [#uses=1] ret i16 %div -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: imull $1986, %eax, % } define i32 @test5(i32 %A) nounwind { %tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1] ret i32 %tmp1 -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: movl $365384439, %eax ; CHECK: mull 4(%esp) } @@ -55,7 +55,7 @@ define signext i16 @test6(i16 signext %x) nounwind { entry: %div = sdiv i16 %x, 10 ret i16 %div -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: imull $26215, %eax, %ecx ; CHECK: sarl $18, %ecx ; CHECK: shrl $15, %eax @@ -64,7 +64,7 @@ entry: define i32 @test7(i32 %x) nounwind { %div = udiv i32 %x, 28 ret i32 %div -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: shrl $2 ; CHECK: movl $613566757 ; CHECK: mull @@ -76,7 +76,7 @@ define i32 @test7(i32 %x) nounwind { define i8 @test8(i8 %x) nounwind { %div = udiv i8 %x, 78 ret i8 %div -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: shrb % ; CHECK: imull $211 ; CHECK: shrl $13 @@ -86,7 +86,7 @@ define i8 @test8(i8 %x) nounwind { define i8 @test9(i8 %x) nounwind { %div = udiv i8 %x, 116 ret i8 %div -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: shrb $2 ; CHECK: imull $71 ; CHECK: shrl $11 diff --git a/llvm/test/CodeGen/X86/fabs.ll b/llvm/test/CodeGen/X86/fabs.ll index af1867fc51c..e330ee79430 100644 --- a/llvm/test/CodeGen/X86/fabs.ll +++ b/llvm/test/CodeGen/X86/fabs.ll @@ -7,9 +7,9 @@ declare float @fabsf(float) declare x86_fp80 @fabsl(x86_fp80) -; CHECK: test1: -; UNSAFE: test1: -; NOOPT: test1: +; CHECK-LABEL: test1: +; UNSAFE-LABEL: test1: +; NOOPT-LABEL: test1: define float @test1(float %X) { %Y = call float @fabsf(float %X) readnone ret float %Y @@ -21,9 +21,9 @@ define float @test1(float %X) { ; UNSAFE-NOT: fabs ; NOOPT-NOT: fabsf -; CHECK: test2: -; UNSAFE: test2: -; NOOPT: test2: +; CHECK-LABEL: test2: +; UNSAFE-LABEL: test2: +; NOOPT-LABEL: test2: define double @test2(double %X) { %Y = fcmp oge double %X, -0.0 %Z = fsub double -0.0, %X @@ -38,9 +38,9 @@ define double @test2(double %X) { ; UNSAFE-NOT: fabs -; CHECK: test3: -; UNSAFE: test3: -; NOOPT: test3: +; CHECK-LABEL: test3: +; UNSAFE-LABEL: test3: +; NOOPT-LABEL: test3: define x86_fp80 @test3(x86_fp80 %X) { %Y = call x86_fp80 @fabsl(x86_fp80 %X) readnone ret x86_fp80 %Y diff --git a/llvm/test/CodeGen/X86/fast-isel-call.ll b/llvm/test/CodeGen/X86/fast-isel-call.ll index 3159741cd9c..42d2b8bed65 100644 --- a/llvm/test/CodeGen/X86/fast-isel-call.ll +++ b/llvm/test/CodeGen/X86/fast-isel-call.ll @@ -10,7 +10,7 @@ BB1: ret i32 1 BB2: ret i32 0 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: calll ; CHECK-NEXT: testb $1 } @@ -21,7 +21,7 @@ declare void @foo2(%struct.s* byval) define void @test2(%struct.s* %d) nounwind { call void @foo2(%struct.s* byval %d ) ret void -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl (%eax) ; CHECK: movl {{.*}}, (%esp) ; CHECK: movl 4(%eax) @@ -35,7 +35,7 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind define void @test3(i8* %a) { call void @llvm.memset.p0i8.i32(i8* %a, i8 0, i32 100, i32 1, i1 false) ret void -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movl {{.*}}, (%esp) ; CHECK: movl $0, 4(%esp) ; CHECK: movl $100, 8(%esp) @@ -47,7 +47,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, define void @test4(i8* %a, i8* %b) { call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 100, i32 1, i1 false) ret void -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movl {{.*}}, (%esp) ; CHECK: movl {{.*}}, 4(%esp) ; CHECK: movl $100, 8(%esp) diff --git a/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll b/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll index f2afaa06bbe..0fd0561e204 100644 --- a/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll +++ b/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll @@ -6,7 +6,7 @@ entry: ret i64 %result } -; CHECK: test_sdiv64: +; CHECK-LABEL: test_sdiv64: ; CHECK: cqto ; CHECK: idivq @@ -16,7 +16,7 @@ entry: ret i64 %result } -; CHECK: test_srem64: +; CHECK-LABEL: test_srem64: ; CHECK: cqto ; CHECK: idivq @@ -26,7 +26,7 @@ entry: ret i64 %result } -; CHECK: test_udiv64: +; CHECK-LABEL: test_udiv64: ; CHECK: xorl ; CHECK: divq @@ -36,6 +36,6 @@ entry: ret i64 %result } -; CHECK: test_urem64: +; CHECK-LABEL: test_urem64: ; CHECK: xorl ; CHECK: divq diff --git a/llvm/test/CodeGen/X86/fast-isel-divrem.ll b/llvm/test/CodeGen/X86/fast-isel-divrem.ll index 1a309a1ebc4..5828becb3c3 100644 --- a/llvm/test/CodeGen/X86/fast-isel-divrem.ll +++ b/llvm/test/CodeGen/X86/fast-isel-divrem.ll @@ -7,7 +7,7 @@ entry: ret i8 %result } -; CHECK: test_sdiv8: +; CHECK-LABEL: test_sdiv8: ; CHECK: movsbw ; CHECK: idivb @@ -17,7 +17,7 @@ entry: ret i8 %result } -; CHECK: test_srem8: +; CHECK-LABEL: test_srem8: ; CHECK: movsbw ; CHECK: idivb @@ -27,7 +27,7 @@ entry: ret i8 %result } -; CHECK: test_udiv8: +; CHECK-LABEL: test_udiv8: ; CHECK: movzbw ; CHECK: divb @@ -37,7 +37,7 @@ entry: ret i8 %result } -; CHECK: test_urem8: +; CHECK-LABEL: test_urem8: ; CHECK: movzbw ; CHECK: divb @@ -47,7 +47,7 @@ entry: ret i16 %result } -; CHECK: test_sdiv16: +; CHECK-LABEL: test_sdiv16: ; CHECK: cwtd ; CHECK: idivw @@ -57,7 +57,7 @@ entry: ret i16 %result } -; CHECK: test_srem16: +; CHECK-LABEL: test_srem16: ; CHECK: cwtd ; CHECK: idivw @@ -67,7 +67,7 @@ entry: ret i16 %result } -; CHECK: test_udiv16: +; CHECK-LABEL: test_udiv16: ; CHECK: xorl ; CHECK: divw @@ -77,7 +77,7 @@ entry: ret i16 %result } -; CHECK: test_urem16: +; CHECK-LABEL: test_urem16: ; CHECK: xorl ; CHECK: divw @@ -87,7 +87,7 @@ entry: ret i32 %result } -; CHECK: test_sdiv32: +; CHECK-LABEL: test_sdiv32: ; CHECK: cltd ; CHECK: idivl @@ -97,7 +97,7 @@ entry: ret i32 %result } -; CHECK: test_srem32: +; CHECK-LABEL: test_srem32: ; CHECK: cltd ; CHECK: idivl @@ -107,7 +107,7 @@ entry: ret i32 %result } -; CHECK: test_udiv32: +; CHECK-LABEL: test_udiv32: ; CHECK: xorl ; CHECK: divl @@ -117,6 +117,6 @@ entry: ret i32 %result } -; CHECK: test_urem32: +; CHECK-LABEL: test_urem32: ; CHECK: xorl ; CHECK: divl diff --git a/llvm/test/CodeGen/X86/fast-isel-extract.ll b/llvm/test/CodeGen/X86/fast-isel-extract.ll index f63396e40ca..3a4b2a68550 100644 --- a/llvm/test/CodeGen/X86/fast-isel-extract.ll +++ b/llvm/test/CodeGen/X86/fast-isel-extract.ll @@ -10,7 +10,7 @@ define void @test1(i64*) nounwind ssp { %4 = add i64 %3, 10 store i64 %4, i64* %0 ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: callq _f ; CHECK-NEXT: addq $10, %rax } @@ -21,7 +21,7 @@ define void @test2(i64*) nounwind ssp { %4 = add i64 %3, 10 store i64 %4, i64* %0 ret void -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: callq _f ; CHECK-NEXT: addq $10, %rdx } diff --git a/llvm/test/CodeGen/X86/fast-isel-gep.ll b/llvm/test/CodeGen/X86/fast-isel-gep.ll index f0375f86028..4e47c7455c5 100644 --- a/llvm/test/CodeGen/X86/fast-isel-gep.ll +++ b/llvm/test/CodeGen/X86/fast-isel-gep.ll @@ -9,11 +9,11 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind { %t9 = getelementptr i32* %t1, i32 %t3 ; <i32*> [#uses=1] %t15 = load i32* %t9 ; <i32> [#uses=1] ret i32 %t15 -; X32: test1: +; X32-LABEL: test1: ; X32: movl (%eax,%ecx,4), %eax ; X32: ret -; X64: test1: +; X64-LABEL: test1: ; X64: movslq %e[[A0:di|cx]], %rax ; X64: movl (%r[[A1:si|dx]],%rax,4), %eax ; X64: ret @@ -23,11 +23,11 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind { %t9 = getelementptr i32* %t1, i64 %t3 ; <i32*> [#uses=1] %t15 = load i32* %t9 ; <i32> [#uses=1] ret i32 %t15 -; X32: test2: +; X32-LABEL: test2: ; X32: movl (%edx,%ecx,4), %e ; X32: ret -; X64: test2: +; X64-LABEL: test2: ; X64: movl (%r[[A1]],%r[[A0]],4), %eax ; X64: ret } @@ -42,12 +42,12 @@ entry: ret i8 %B -; X32: test3: +; X32-LABEL: test3: ; X32: movl 4(%esp), %eax ; X32: movb -2(%eax), %al ; X32: ret -; X64: test3: +; X64-LABEL: test3: ; X64: movb -2(%r[[A0]]), %al ; X64: ret @@ -66,9 +66,9 @@ entry: %tmp2 = load double* %arrayidx ; <double> [#uses=1] ret double %tmp2 -; X32: test4: +; X32-LABEL: test4: ; X32: 128(%e{{.*}},%e{{.*}},8) -; X64: test4: +; X64-LABEL: test4: ; X64: 128(%r{{.*}},%r{{.*}},8) } @@ -80,7 +80,7 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { %v10 = load i64* %v9 %v11 = add i64 %B, %v10 ret i64 %v11 -; X64: test5: +; X64-LABEL: test5: ; X64: movslq %e[[A1]], %rax ; X64-NEXT: (%r[[A0]],%rax), ; X64: ret @@ -113,7 +113,7 @@ declare i8* @_ZNK18G__FastAllocString4dataEv() nounwind ; PR10605 / rdar://9930964 - Don't fold loads incorrectly. The load should ; happen before the store. define i32 @test7({i32,i32,i32}* %tmp1, i32 %tmp71, i32 %tmp63) nounwind { -; X64: test7: +; X64-LABEL: test7: ; X64: movl 8({{%rdi|%rcx}}), %eax ; X64: movl $4, 8({{%rdi|%rcx}}) diff --git a/llvm/test/CodeGen/X86/fast-isel-i1.ll b/llvm/test/CodeGen/X86/fast-isel-i1.ll index bea18a19500..9c042d30e78 100644 --- a/llvm/test/CodeGen/X86/fast-isel-i1.ll +++ b/llvm/test/CodeGen/X86/fast-isel-i1.ll @@ -4,7 +4,7 @@ declare i32 @test1a(i32) define i32 @test1(i32 %x) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: andb $1, % %y = add i32 %x, -3 %t = call i32 @test1a(i32 %y) @@ -23,7 +23,7 @@ exit: ; preds = %next define void @test2(i8* %a) nounwind { entry: -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movb {{.*}} %al ; CHECK-NEXT: xorb $1, %al ; CHECK-NEXT: testb $1 diff --git a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll index ad1520ef819..f7d2750b5b8 100644 --- a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll +++ b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll @@ -11,7 +11,7 @@ define i32 @test1(i32 %i) nounwind ssp { ret i32 %and } -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: andl $8, @@ -29,7 +29,7 @@ if.then: ; preds = %entry if.end: ; preds = %if.then, %entry ret void -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movq %rdi, -8(%rsp) ; CHECK: cmpq $42, -8(%rsp) } @@ -41,7 +41,7 @@ if.end: ; preds = %if.then, %entry define i64 @test3() nounwind { %A = ptrtoint i32* @G to i64 ret i64 %A -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movq _G@GOTPCREL(%rip), %rax ; CHECK-NEXT: ret } @@ -57,7 +57,7 @@ define i32 @test4(i64 %idxprom9) nounwind { %conv = zext i8 %tmp11 to i32 ret i32 %conv -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movq _rtx_length@GOTPCREL(%rip), %rax ; CHECK-NEXT: movzbl (%rax,%rdi), %eax ; CHECK-NEXT: ret @@ -70,7 +70,7 @@ define void @test5(i32 %x, i32* %p) nounwind { store i32 %y, i32* %p ret void -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: movl $50000, %ecx ; CHECK: sarl %cl, %edi ; CHECK: ret @@ -82,7 +82,7 @@ entry: %mul = mul nsw i64 %x, 8 ret i64 %mul -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: shlq $3, %rdi } @@ -90,7 +90,7 @@ define i32 @test7(i32 %x) nounwind ssp { entry: %mul = mul nsw i32 %x, 8 ret i32 %mul -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: shll $3, %edi } @@ -101,7 +101,7 @@ entry: %add = add nsw i64 %x, 7 ret i64 %add -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: addq $7, %rdi } @@ -109,7 +109,7 @@ define i64 @test9(i64 %x) nounwind ssp { entry: %add = mul nsw i64 %x, 7 ret i64 %add -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: imulq $7, %rdi, %rax } @@ -117,14 +117,14 @@ entry: define i32 @test10(i32 %X) nounwind { %Y = udiv i32 %X, 8 ret i32 %Y -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: shrl $3, } define i32 @test11(i32 %X) nounwind { %Y = sdiv exact i32 %X, 8 ret i32 %Y -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: sarl $3, } @@ -141,7 +141,7 @@ if.then: ; preds = %entry if.end: ; preds = %if.then, %entry ret void -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: testb $1, ; CHECK-NEXT: je L ; CHECK-NEXT: movl $0, %edi @@ -153,7 +153,7 @@ declare void @test13f(i1 %X) define void @test13() nounwind { call void @test13f(i1 0) ret void -; CHECK: test13: +; CHECK-LABEL: test13: ; CHECK: movl $0, %edi ; CHECK-NEXT: callq } @@ -166,7 +166,7 @@ entry: %tobool = trunc i8 %tmp to i1 call void @test13f(i1 zeroext %tobool) noredzone ret void -; CHECK: test14: +; CHECK-LABEL: test14: ; CHECK: andb $1, ; CHECK: callq } @@ -177,7 +177,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) define void @test15(i8* %a, i8* %b) nounwind { call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false) ret void -; CHECK: test15: +; CHECK-LABEL: test15: ; CHECK-NEXT: movl (%rsi), %eax ; CHECK-NEXT: movl %eax, (%rdi) ; CHECK-NEXT: ret @@ -186,7 +186,7 @@ define void @test15(i8* %a, i8* %b) nounwind { ; Handling for varargs calls declare void @test16callee(...) nounwind define void @test16() nounwind { -; CHECK: test16: +; CHECK-LABEL: test16: ; CHECK: movl $1, %edi ; CHECK: movb $0, %al ; CHECK: callq _test16callee @@ -224,7 +224,7 @@ if.then: ; preds = %entry if.else: ; preds = %entry ret i32 2 -; CHECK: test17: +; CHECK-LABEL: test17: ; CHECK: movl (%rdi), %eax ; CHECK: callq _foo ; CHECK: cmpl $5, %eax @@ -235,7 +235,7 @@ if.else: ; preds = %entry define void @test18(float* %p1) { store float 0.0, float* %p1 ret void -; CHECK: test18: +; CHECK-LABEL: test18: ; CHECK: xorps } @@ -243,7 +243,7 @@ define void @test18(float* %p1) { define void @test19(double* %p1) { store double 0.0, double* %p1 ret void -; CHECK: test19: +; CHECK-LABEL: test19: ; CHECK: xorps } @@ -254,7 +254,7 @@ entry: %tmp = alloca %struct.a, align 8 call void @test20sret(%struct.a* sret %tmp) ret void -; CHECK: test20: +; CHECK-LABEL: test20: ; CHECK: leaq (%rsp), %rdi ; CHECK: callq _test20sret } @@ -264,7 +264,7 @@ declare void @test20sret(%struct.a* sret) define void @test21(double* %p1) { store double -0.0, double* %p1 ret void -; CHECK: test21: +; CHECK-LABEL: test21: ; CHECK-NOT: xor ; CHECK: movsd LCPI } @@ -279,7 +279,7 @@ entry: call void @foo22(i32 2) call void @foo22(i32 3) ret void -; CHECK: test22: +; CHECK-LABEL: test22: ; CHECK: movl $0, %edi ; CHECK: callq _foo22 ; CHECK: movl $1, %edi @@ -297,7 +297,7 @@ define void @test23(i8* noalias sret %result) { %a = alloca i8 %b = call i8* @foo23() ret void -; CHECK: test23: +; CHECK-LABEL: test23: ; CHECK: call ; CHECK: movq %rdi, %rax ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/fast-isel-x86.ll b/llvm/test/CodeGen/X86/fast-isel-x86.ll index 4caa3a039d6..ba86e888cdd 100644 --- a/llvm/test/CodeGen/X86/fast-isel-x86.ll +++ b/llvm/test/CodeGen/X86/fast-isel-x86.ll @@ -1,7 +1,7 @@ ; RUN: llc -fast-isel -O0 -mcpu=generic -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s ; This should use flds to set the return value. -; CHECK: test0: +; CHECK-LABEL: test0: ; CHECK: flds ; CHECK: ret @G = external global float @@ -11,7 +11,7 @@ define float @test0() nounwind { } ; This should pop 4 bytes on return. -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: ret $4 define void @test1({i32, i32, i32, i32}* sret %p) nounwind { store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p @@ -19,7 +19,7 @@ define void @test1({i32, i32, i32, i32}* sret %p) nounwind { } ; Properly initialize the pic base. -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK-NOT: HHH ; CHECK: call{{.*}}L2$pb ; CHECK-NEXT: L2$pb: @@ -39,7 +39,7 @@ entry: %tmp = alloca %struct.a, align 8 call void @test3sret(%struct.a* sret %tmp) ret void -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: subl $44 ; CHECK: leal 16(%esp) ; CHECK: calll _test3sret @@ -53,7 +53,7 @@ entry: %tmp = alloca %struct.a, align 8 call fastcc void @test4fastccsret(%struct.a* sret %tmp) ret void -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: subl $28 ; CHECK: leal (%esp), %ecx ; CHECK: calll _test4fastccsret diff --git a/llvm/test/CodeGen/X86/fold-load.ll b/llvm/test/CodeGen/X86/fold-load.ll index d8366654c01..495acd990df 100644 --- a/llvm/test/CodeGen/X86/fold-load.ll +++ b/llvm/test/CodeGen/X86/fold-load.ll @@ -39,7 +39,7 @@ L: store i16 %A, i16* %Q ret i32 %D -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: movzwl (%eax), %ecx @@ -48,7 +48,7 @@ L: ; rdar://10554090 ; xor in exit block will be CSE'ed and load will be folded to xor in entry. define i1 @test3(i32* %P, i32* %Q) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movl 8(%esp), %eax ; CHECK: xorl (%eax), ; CHECK: j diff --git a/llvm/test/CodeGen/X86/iabs.ll b/llvm/test/CodeGen/X86/iabs.ll index 9196cce1ae5..f47bd7b2def 100644 --- a/llvm/test/CodeGen/X86/iabs.ll +++ b/llvm/test/CodeGen/X86/iabs.ll @@ -7,7 +7,7 @@ ;; ret ; rdar://10695237 define i32 @test(i32 %a) nounwind { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: mov ; CHECK-NEXT: neg ; CHECK-NEXT: cmov diff --git a/llvm/test/CodeGen/X86/isel-sink.ll b/llvm/test/CodeGen/X86/isel-sink.ll index d2755331fe8..458f19dfc4f 100644 --- a/llvm/test/CodeGen/X86/isel-sink.ll +++ b/llvm/test/CodeGen/X86/isel-sink.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i32* %X, i32 %B) { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK-NOT: lea ; CHECK: mov{{.}} $4, ({{.*}},{{.*}},4) diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll index 0e34222b945..91ac94222a4 100644 --- a/llvm/test/CodeGen/X86/jump_sign.ll +++ b/llvm/test/CodeGen/X86/jump_sign.ll @@ -283,7 +283,7 @@ entry: @a = common global i32 0, align 4 define i32 @test1(i32 %p1) nounwind uwtable { entry: -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: testb ; CHECK: j ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/lea.ll b/llvm/test/CodeGen/X86/lea.ll index 87f0b0b30a8..affd6bf3bb8 100644 --- a/llvm/test/CodeGen/X86/lea.ll +++ b/llvm/test/CodeGen/X86/lea.ll @@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind { %tmp1 = shl i32 %x, 3 %tmp2 = add i32 %tmp1, 7 ret i32 %tmp2 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: leal 7(,%r[[A0:di|cx]],8), %eax } @@ -27,7 +27,7 @@ bb.nph: bb2: ret i32 %x_offs -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl %e[[A0]], %eax ; CHECK: addl $-5, %eax ; CHECK: andl $-4, %eax diff --git a/llvm/test/CodeGen/X86/legalize-shift-64.ll b/llvm/test/CodeGen/X86/legalize-shift-64.ll index 0e6fb1366aa..748cbcb82f3 100644 --- a/llvm/test/CodeGen/X86/legalize-shift-64.ll +++ b/llvm/test/CodeGen/X86/legalize-shift-64.ll @@ -6,7 +6,7 @@ define i64 @test1(i32 %xx, i32 %test) nounwind { %sh_prom = zext i32 %and to i64 %shl = shl i64 %conv, %sh_prom ret i64 %shl -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: shll %cl, %eax ; CHECK: shrl %edx ; CHECK: xorb $31 @@ -18,7 +18,7 @@ define i64 @test2(i64 %xx, i32 %test) nounwind { %sh_prom = zext i32 %and to i64 %shl = shl i64 %xx, %sh_prom ret i64 %shl -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: shll %cl, %esi ; CHECK: shrl %edx ; CHECK: xorb $31 @@ -32,7 +32,7 @@ define i64 @test3(i64 %xx, i32 %test) nounwind { %sh_prom = zext i32 %and to i64 %shr = lshr i64 %xx, %sh_prom ret i64 %shr -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: shrl %cl, %esi ; CHECK: leal (%edx,%edx), %eax ; CHECK: xorb $31, %cl @@ -46,7 +46,7 @@ define i64 @test4(i64 %xx, i32 %test) nounwind { %sh_prom = zext i32 %and to i64 %shr = ashr i64 %xx, %sh_prom ret i64 %shr -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: shrl %cl, %esi ; CHECK: leal (%edx,%edx), %eax ; CHECK: xorb $31, %cl diff --git a/llvm/test/CodeGen/X86/longlong-deadload.ll b/llvm/test/CodeGen/X86/longlong-deadload.ll index db91961e041..73e10127c06 100644 --- a/llvm/test/CodeGen/X86/longlong-deadload.ll +++ b/llvm/test/CodeGen/X86/longlong-deadload.ll @@ -2,7 +2,7 @@ ; This should not load or store the top part of *P. define void @test(i64* %P) nounwind { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: movl 4(%esp), %[[REGISTER:.*]] ; CHECK-NOT: 4(%[[REGISTER]]) ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/lsr-reuse.ll b/llvm/test/CodeGen/X86/lsr-reuse.ll index 1311a73fd32..a26745008b1 100644 --- a/llvm/test/CodeGen/X86/lsr-reuse.ll +++ b/llvm/test/CodeGen/X86/lsr-reuse.ll @@ -447,7 +447,7 @@ bb5: ; preds = %bb3, %entry ; we don't want to leave extra induction variables around, or use an ; lea to compute an exit condition inside the loop: -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: BB10_4: ; CHECK-NEXT: movaps %xmm{{.*}}, %xmm{{.*}} diff --git a/llvm/test/CodeGen/X86/memcpy.ll b/llvm/test/CodeGen/X86/memcpy.ll index 3372a4adc5e..88b6cfd2295 100644 --- a/llvm/test/CodeGen/X86/memcpy.ll +++ b/llvm/test/CodeGen/X86/memcpy.ll @@ -10,7 +10,7 @@ entry: tail call void @llvm.memcpy.p0i8.p0i8.i64( i8* %a, i8* %b, i64 %n, i32 1, i1 0 ) ret i8* %a -; LINUX: test1: +; LINUX-LABEL: test1: ; LINUX: memcpy } @@ -22,7 +22,7 @@ entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8, i1 0 ) ret i8* %tmp14 -; LINUX: test2: +; LINUX-LABEL: test2: ; LINUX: memcpy } @@ -36,10 +36,10 @@ define void @test3(i8* nocapture %A, i8* nocapture %B) nounwind optsize noredzon entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false) ret void -; LINUX: test3: +; LINUX-LABEL: test3: ; LINUX: memcpy -; DARWIN: test3: +; DARWIN-LABEL: test3: ; DARWIN-NOT: memcpy ; DARWIN: movq ; DARWIN: movq @@ -64,7 +64,7 @@ define void @test4(i8* nocapture %A, i8* nocapture %B) nounwind noredzone { entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false) ret void -; LINUX: test4: +; LINUX-LABEL: test4: ; LINUX: movq ; LINUX: movq ; LINUX: movq @@ -87,7 +87,7 @@ entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false) ret void -; DARWIN: test5: +; DARWIN-LABEL: test5: ; DARWIN: movabsq $7016996765293437281 ; DARWIN: movabsq $7016996765293437184 } diff --git a/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll b/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll index df9de5dfaf2..d77a7ed3816 100644 --- a/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll +++ b/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll @@ -14,26 +14,26 @@ define void @test1(i32 %t) nounwind { call void @dummy(i8* %x) ret void -; NOSSE: test1: +; NOSSE-LABEL: test1: ; NOSSE-NOT: and ; NOSSE: movl $0 -; SSE1: test1: +; SSE1-LABEL: test1: ; SSE1: andl $-16 ; SSE1: movl %esp, %esi ; SSE1: movaps -; SSE2: test1: +; SSE2-LABEL: test1: ; SSE2: andl $-16 ; SSE2: movl %esp, %esi ; SSE2: movaps -; AVX1: test1: +; AVX1-LABEL: test1: ; AVX1: andl $-32 ; AVX1: movl %esp, %esi ; AVX1: vmovaps %ymm -; AVX2: test1: +; AVX2-LABEL: test1: ; AVX2: andl $-32 ; AVX2: movl %esp, %esi ; AVX2: vmovaps %ymm @@ -47,26 +47,26 @@ define void @test2(i32 %t) nounwind { call void @dummy(i8* %x) ret void -; NOSSE: test2: +; NOSSE-LABEL: test2: ; NOSSE-NOT: and ; NOSSE: movl $0 -; SSE1: test2: +; SSE1-LABEL: test2: ; SSE1: andl $-16 ; SSE1: movl %esp, %esi ; SSE1: movaps -; SSE2: test2: +; SSE2-LABEL: test2: ; SSE2: andl $-16 ; SSE2: movl %esp, %esi ; SSE2: movaps -; AVX1: test2: +; AVX1-LABEL: test2: ; AVX1: andl $-16 ; AVX1: movl %esp, %esi ; AVX1: vmovaps %xmm -; AVX2: test2: +; AVX2-LABEL: test2: ; AVX2: andl $-16 ; AVX2: movl %esp, %esi ; AVX2: vmovaps %xmm diff --git a/llvm/test/CodeGen/X86/movbe.ll b/llvm/test/CodeGen/X86/movbe.ll index 3d3d8cf19b7..aa58c1060e7 100644 --- a/llvm/test/CodeGen/X86/movbe.ll +++ b/llvm/test/CodeGen/X86/movbe.ll @@ -7,7 +7,7 @@ define void @test1(i32* nocapture %x, i32 %y) nounwind { %bswap = call i32 @llvm.bswap.i32(i32 %y) store i32 %bswap, i32* %x, align 4 ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movbel %esi, (%rdi) } @@ -15,7 +15,7 @@ define i32 @test2(i32* %x) nounwind { %load = load i32* %x, align 4 %bswap = call i32 @llvm.bswap.i32(i32 %load) ret i32 %bswap -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movbel (%rdi), %eax } @@ -23,7 +23,7 @@ define void @test3(i64* %x, i64 %y) nounwind { %bswap = call i64 @llvm.bswap.i64(i64 %y) store i64 %bswap, i64* %x, align 8 ret void -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movbeq %rsi, (%rdi) } @@ -31,6 +31,6 @@ define i64 @test4(i64* %x) nounwind { %load = load i64* %x, align 8 %bswap = call i64 @llvm.bswap.i64(i64 %load) ret i64 %bswap -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movbeq (%rdi), %rax } diff --git a/llvm/test/CodeGen/X86/movgs.ll b/llvm/test/CodeGen/X86/movgs.ll index bb42734833d..e5afb2753e3 100644 --- a/llvm/test/CodeGen/X86/movgs.ll +++ b/llvm/test/CodeGen/X86/movgs.ll @@ -8,12 +8,12 @@ entry: %tmp1 = load i32* %tmp ; <i32> [#uses=1] ret i32 %tmp1 } -; X32: test1: +; X32-LABEL: test1: ; X32: movl %gs:196, %eax ; X32: movl (%eax), %eax ; X32: ret -; X64: test1: +; X64-LABEL: test1: ; X64: movq %gs:320, %rax ; X64: movl (%rax), %eax ; X64: ret @@ -26,11 +26,11 @@ entry: } ; rdar://8453210 -; X32: test2: +; X32-LABEL: test2: ; X32: movl {{.*}}(%esp), %eax ; X32: calll *%gs:(%eax) -; X64: test2: +; X64-LABEL: test2: ; X64: callq *%gs:([[A0:%rdi|%rcx]]) @@ -66,7 +66,7 @@ entry: %tmp4 = add i32 %tmp1, %tmp3 ret i32 %tmp4 } -; X32: test_no_cse: +; X32-LABEL: test_no_cse: ; X32: movl %gs:196 ; X32: movl %fs:196 ; X32: ret diff --git a/llvm/test/CodeGen/X86/narrow-shl-cst.ll b/llvm/test/CodeGen/X86/narrow-shl-cst.ll index a404f34b9ca..40b976014a7 100644 --- a/llvm/test/CodeGen/X86/narrow-shl-cst.ll +++ b/llvm/test/CodeGen/X86/narrow-shl-cst.ll @@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind { %and = shl i32 %x, 10 %shl = and i32 %and, 31744 ret i32 %shl -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: andl $31 ; CHECK: shll $10 } @@ -14,7 +14,7 @@ define i32 @test2(i32 %x) nounwind { %or = shl i32 %x, 10 %shl = or i32 %or, 31744 ret i32 %shl -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: orl $31 ; CHECK: shll $10 } @@ -23,7 +23,7 @@ define i32 @test3(i32 %x) nounwind { %xor = shl i32 %x, 10 %shl = xor i32 %xor, 31744 ret i32 %shl -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: xorl $31 ; CHECK: shll $10 } @@ -32,7 +32,7 @@ define i64 @test4(i64 %x) nounwind { %and = shl i64 %x, 40 %shl = and i64 %and, 264982302294016 ret i64 %shl -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: andq $241 ; CHECK: shlq $40 } @@ -41,7 +41,7 @@ define i64 @test5(i64 %x) nounwind { %and = shl i64 %x, 40 %shl = and i64 %and, 34084860461056 ret i64 %shl -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: andq $31 ; CHECK: shlq $40 } @@ -50,7 +50,7 @@ define i64 @test6(i64 %x) nounwind { %and = shl i64 %x, 32 %shl = and i64 %and, -281474976710656 ret i64 %shl -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: andq $-65536 ; CHECK: shlq $32 } @@ -59,7 +59,7 @@ define i64 @test7(i64 %x) nounwind { %or = shl i64 %x, 40 %shl = or i64 %or, 264982302294016 ret i64 %shl -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: orq $241 ; CHECK: shlq $40 } @@ -68,7 +68,7 @@ define i64 @test8(i64 %x) nounwind { %or = shl i64 %x, 40 %shl = or i64 %or, 34084860461056 ret i64 %shl -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: orq $31 ; CHECK: shlq $40 } @@ -77,7 +77,7 @@ define i64 @test9(i64 %x) nounwind { %xor = shl i64 %x, 40 %shl = xor i64 %xor, 264982302294016 ret i64 %shl -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: orq $241 ; CHECK: shlq $40 } @@ -86,7 +86,7 @@ define i64 @test10(i64 %x) nounwind { %xor = shl i64 %x, 40 %shl = xor i64 %xor, 34084860461056 ret i64 %shl -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: xorq $31 ; CHECK: shlq $40 } @@ -95,7 +95,7 @@ define i64 @test11(i64 %x) nounwind { %xor = shl i64 %x, 33 %shl = xor i64 %xor, -562949953421312 ret i64 %shl -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: xorq $-65536 ; CHECK: shlq $33 } diff --git a/llvm/test/CodeGen/X86/narrow-shl-load.ll b/llvm/test/CodeGen/X86/narrow-shl-load.ll index 7822453add4..30387925b34 100644 --- a/llvm/test/CodeGen/X86/narrow-shl-load.ll +++ b/llvm/test/CodeGen/X86/narrow-shl-load.ll @@ -33,7 +33,7 @@ while.end: ; preds = %while.cond ; DAGCombiner shouldn't fold the sdiv (ashr) away. ; rdar://8636812 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: sarl define i32 @test2() nounwind { diff --git a/llvm/test/CodeGen/X86/no-cmov.ll b/llvm/test/CodeGen/X86/no-cmov.ll index 62d73b0732e..e13edf26cad 100644 --- a/llvm/test/CodeGen/X86/no-cmov.ll +++ b/llvm/test/CodeGen/X86/no-cmov.ll @@ -6,6 +6,6 @@ define i32 @test1(i32 %g, i32* %j) { %retval.0 = select i1 %tobool, i32 1, i32 %cmp ret i32 %retval.0 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: cmov } diff --git a/llvm/test/CodeGen/X86/or-address.ll b/llvm/test/CodeGen/X86/or-address.ll index f866e419c30..6bea864027b 100644 --- a/llvm/test/CodeGen/X86/or-address.ll +++ b/llvm/test/CodeGen/X86/or-address.ll @@ -46,7 +46,7 @@ return: ; preds = %bb ret void } -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4) ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4) ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4) diff --git a/llvm/test/CodeGen/X86/palignr.ll b/llvm/test/CodeGen/X86/palignr.ll index 6875fb33924..c76cbbe2e37 100644 --- a/llvm/test/CodeGen/X86/palignr.ll +++ b/llvm/test/CodeGen/X86/palignr.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: pshufd ; CHECK-YONAH: pshufd %C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 > @@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { } define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: palignr ; CHECK-YONAH: shufps %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 > @@ -18,42 +18,42 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { } define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: palignr %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 > ret <4 x i32> %C } define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: palignr %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 > ret <4 x i32> %C } define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: palignr %C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 > ret <4 x float> %C } define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: palignr %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 > ret <8 x i16> %C } define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind { -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: palignr %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 > ret <8 x i16> %C } define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind { -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: palignr %C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 > ret <16 x i8> %C @@ -64,7 +64,7 @@ define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind { ; incorrectly. In particular, one of the operands of the palignr node ; was an UNDEF.) define <8 x i16> @test9(<8 x i16> %A, <8 x i16> %B) nounwind { -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK-NOT: palignr ; CHECK: pshufb %C = shufflevector <8 x i16> %B, <8 x i16> %A, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 > diff --git a/llvm/test/CodeGen/X86/peep-setb.ll b/llvm/test/CodeGen/X86/peep-setb.ll index 0bab7890763..adae8acd043 100644 --- a/llvm/test/CodeGen/X86/peep-setb.ll +++ b/llvm/test/CodeGen/X86/peep-setb.ll @@ -5,7 +5,7 @@ define i8 @test1(i8 %a, i8 %b) nounwind { %cond = zext i1 %cmp to i8 %add = add i8 %cond, %b ret i8 %add -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: adcb $0 } @@ -14,7 +14,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind { %cond = zext i1 %cmp to i32 %add = add i32 %cond, %b ret i32 %add -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: adcl $0 } @@ -23,7 +23,7 @@ define i64 @test3(i64 %a, i64 %b) nounwind { %conv = zext i1 %cmp to i64 %add = add i64 %conv, %b ret i64 %add -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: adcq $0 } @@ -32,7 +32,7 @@ define i8 @test4(i8 %a, i8 %b) nounwind { %cond = zext i1 %cmp to i8 %sub = sub i8 %b, %cond ret i8 %sub -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: sbbb $0 } @@ -41,7 +41,7 @@ define i32 @test5(i32 %a, i32 %b) nounwind { %cond = zext i1 %cmp to i32 %sub = sub i32 %b, %cond ret i32 %sub -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: sbbl $0 } @@ -50,7 +50,7 @@ define i64 @test6(i64 %a, i64 %b) nounwind { %conv = zext i1 %cmp to i64 %sub = sub i64 %b, %conv ret i64 %sub -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: sbbq $0 } @@ -59,7 +59,7 @@ define i8 @test7(i8 %a, i8 %b) nounwind { %cond = sext i1 %cmp to i8 %sub = sub i8 %b, %cond ret i8 %sub -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: adcb $0 } @@ -68,7 +68,7 @@ define i32 @test8(i32 %a, i32 %b) nounwind { %cond = sext i1 %cmp to i32 %sub = sub i32 %b, %cond ret i32 %sub -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: adcl $0 } @@ -77,6 +77,6 @@ define i64 @test9(i64 %a, i64 %b) nounwind { %conv = sext i1 %cmp to i64 %sub = sub i64 %b, %conv ret i64 %sub -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: adcq $0 } diff --git a/llvm/test/CodeGen/X86/peep-test-3.ll b/llvm/test/CodeGen/X86/peep-test-3.ll index a3799807b38..a7c456a1c9d 100644 --- a/llvm/test/CodeGen/X86/peep-test-3.ll +++ b/llvm/test/CodeGen/X86/peep-test-3.ll @@ -67,7 +67,7 @@ return: ; preds = %entry ; Just like @and, but without the trunc+store. This should use a testb ; instead of an andl. -; CHECK: test: +; CHECK-LABEL: test: define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind { entry: store i8 0, i8* %p diff --git a/llvm/test/CodeGen/X86/pic.ll b/llvm/test/CodeGen/X86/pic.ll index fc0630991c9..7bb127eae93 100644 --- a/llvm/test/CodeGen/X86/pic.ll +++ b/llvm/test/CodeGen/X86/pic.ll @@ -11,7 +11,7 @@ entry: store i32 %tmp.s, i32* @dst ret void -; LINUX: test0: +; LINUX-LABEL: test0: ; LINUX: calll .L0$pb ; LINUX-NEXT: .L0$pb: ; LINUX-NEXT: popl @@ -33,7 +33,7 @@ entry: store i32 %tmp.s, i32* @dst2 ret void -; LINUX: test1: +; LINUX-LABEL: test1: ; LINUX: calll .L1$pb ; LINUX-NEXT: .L1$pb: ; LINUX-NEXT: popl @@ -51,7 +51,7 @@ define void @test2() nounwind { entry: %ptr = call i8* @malloc(i32 40) ret void -; LINUX: test2: +; LINUX-LABEL: test2: ; LINUX: pushl %ebx ; LINUX-NEXT: subl $8, %esp ; LINUX-NEXT: calll .L2$pb @@ -74,7 +74,7 @@ entry: %tmp1 = load void(...)** @pfoo call void(...)* %tmp1() ret void -; LINUX: test3: +; LINUX-LABEL: test3: ; LINUX: calll .L3$pb ; LINUX-NEXT: .L3$pb: ; LINUX: popl @@ -90,7 +90,7 @@ define void @test4() nounwind { entry: call void(...)* @foo() ret void -; LINUX: test4: +; LINUX-LABEL: test4: ; LINUX: calll .L4$pb ; LINUX: popl %ebx ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx @@ -111,7 +111,7 @@ entry: store i32 %tmp.s, i32* @dst6 ret void -; LINUX: test5: +; LINUX-LABEL: test5: ; LINUX: calll .L5$pb ; LINUX-NEXT: .L5$pb: ; LINUX-NEXT: popl %eax @@ -133,7 +133,7 @@ entry: ; LINUX: .LCPI6_0: -; LINUX: test6: +; LINUX-LABEL: test6: ; LINUX: calll .L6$pb ; LINUX: .L6$pb: ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), @@ -185,7 +185,7 @@ bb12: tail call void(...)* @foo6() ret void -; LINUX: test7: +; LINUX-LABEL: test7: ; LINUX: calll .L7$pb ; LINUX: .L7$pb: ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), diff --git a/llvm/test/CodeGen/X86/pmovsx-inreg.ll b/llvm/test/CodeGen/X86/pmovsx-inreg.ll index d8c27f25043..d30d7d0694a 100644 --- a/llvm/test/CodeGen/X86/pmovsx-inreg.ll +++ b/llvm/test/CodeGen/X86/pmovsx-inreg.ll @@ -12,13 +12,13 @@ define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind { store <2 x i64> %sext, <2 x i64>* %out, align 8 ret void -; SSE41: test1: +; SSE41-LABEL: test1: ; SSE41: pmovsxbq -; AVX1: test1: +; AVX1-LABEL: test1: ; AVX1: vpmovsxbq -; AVX2: test1: +; AVX2-LABEL: test1: ; AVX2: vpmovsxbq } @@ -29,7 +29,7 @@ define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind { store <4 x i64> %sext, <4 x i64>* %out, align 8 ret void -; AVX2: test2: +; AVX2-LABEL: test2: ; AVX2: vpmovsxbq } @@ -40,13 +40,13 @@ define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind { store <4 x i32> %sext, <4 x i32>* %out, align 8 ret void -; SSE41: test3: +; SSE41-LABEL: test3: ; SSE41: pmovsxbd -; AVX1: test3: +; AVX1-LABEL: test3: ; AVX1: vpmovsxbd -; AVX2: test3: +; AVX2-LABEL: test3: ; AVX2: vpmovsxbd } @@ -57,7 +57,7 @@ define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind { store <8 x i32> %sext, <8 x i32>* %out, align 8 ret void -; AVX2: test4: +; AVX2-LABEL: test4: ; AVX2: vpmovsxbd } @@ -68,13 +68,13 @@ define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind { store <8 x i16> %sext, <8 x i16>* %out, align 8 ret void -; SSE41: test5: +; SSE41-LABEL: test5: ; SSE41: pmovsxbw -; AVX1: test5: +; AVX1-LABEL: test5: ; AVX1: vpmovsxbw -; AVX2: test5: +; AVX2-LABEL: test5: ; AVX2: vpmovsxbw } @@ -85,7 +85,7 @@ define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind { store <16 x i16> %sext, <16 x i16>* %out, align 8 ret void -; AVX2: test6: +; AVX2-LABEL: test6: ; FIXME: v16i8 -> v16i16 is scalarized. ; AVX2-NOT: pmovsx } @@ -98,13 +98,13 @@ define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind { ret void -; SSE41: test7: +; SSE41-LABEL: test7: ; SSE41: pmovsxwq -; AVX1: test7: +; AVX1-LABEL: test7: ; AVX1: vpmovsxwq -; AVX2: test7: +; AVX2-LABEL: test7: ; AVX2: vpmovsxwq } @@ -115,7 +115,7 @@ define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind { store <4 x i64> %sext, <4 x i64>* %out, align 8 ret void -; AVX2: test8: +; AVX2-LABEL: test8: ; AVX2: vpmovsxwq } @@ -126,13 +126,13 @@ define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind { store <4 x i32> %sext, <4 x i32>* %out, align 8 ret void -; SSE41: test9: +; SSE41-LABEL: test9: ; SSE41: pmovsxwd -; AVX1: test9: +; AVX1-LABEL: test9: ; AVX1: vpmovsxwd -; AVX2: test9: +; AVX2-LABEL: test9: ; AVX2: vpmovsxwd } @@ -143,7 +143,7 @@ define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind { store <8 x i32> %sext, <8 x i32>* %out, align 8 ret void -; AVX2: test10: +; AVX2-LABEL: test10: ; AVX2: vpmovsxwd } @@ -154,13 +154,13 @@ define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind { store <2 x i64> %sext, <2 x i64>* %out, align 8 ret void -; SSE41: test11: +; SSE41-LABEL: test11: ; SSE41: pmovsxdq -; AVX1: test11: +; AVX1-LABEL: test11: ; AVX1: vpmovsxdq -; AVX2: test11: +; AVX2-LABEL: test11: ; AVX2: vpmovsxdq } @@ -171,6 +171,6 @@ define void @test12(<4 x i32>* %in, <4 x i64>* %out) nounwind { store <4 x i64> %sext, <4 x i64>* %out, align 8 ret void -; AVX2: test12: +; AVX2-LABEL: test12: ; AVX2: vpmovsxdq } diff --git a/llvm/test/CodeGen/X86/pmulld.ll b/llvm/test/CodeGen/X86/pmulld.ll index be527aed9a9..4103eabae5f 100644 --- a/llvm/test/CodeGen/X86/pmulld.ll +++ b/llvm/test/CodeGen/X86/pmulld.ll @@ -2,10 +2,10 @@ ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse41 -asm-verbose=0 | FileCheck %s -check-prefix=WIN64 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NEXT: pmulld -; WIN64: test1: +; WIN64-LABEL: test1: ; WIN64-NEXT: movdqa (%rcx), %xmm0 ; WIN64-NEXT: pmulld (%rdx), %xmm0 %C = mul <4 x i32> %A, %B @@ -13,10 +13,10 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { } define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind { -; CHECK: test1a: +; CHECK-LABEL: test1a: ; CHECK-NEXT: pmulld -; WIN64: test1a: +; WIN64-LABEL: test1a: ; WIN64-NEXT: movdqa (%rcx), %xmm0 ; WIN64-NEXT: pmulld (%rdx), %xmm0 diff --git a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll index 0bf601bc1c4..5089bd761a8 100644 --- a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll +++ b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll @@ -179,7 +179,7 @@ return: define void @test3() nounwind ssp { entry: -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: decq 16(%rax) %0 = load i64** @foo, align 8 %arrayidx = getelementptr inbounds i64* %0, i64 2 diff --git a/llvm/test/CodeGen/X86/reverse_branches.ll b/llvm/test/CodeGen/X86/reverse_branches.ll index 97721250377..ee6333e61e8 100644 --- a/llvm/test/CodeGen/X86/reverse_branches.ll +++ b/llvm/test/CodeGen/X86/reverse_branches.ll @@ -7,7 +7,7 @@ ; Make sure at end of do.cond.i, we jump to do.body.i first to have a tighter ; inner loop. define i32 @test_branches_order() uwtable ssp { -; CHECK: test_branches_order: +; CHECK-LABEL: test_branches_order: ; CHECK: [[L0:LBB0_[0-9]+]]: ## %do.body.i ; CHECK: je ; CHECK: %do.cond.i diff --git a/llvm/test/CodeGen/X86/sdiv-exact.ll b/llvm/test/CodeGen/X86/sdiv-exact.ll index 48bb8836e89..4f8d3f05351 100644 --- a/llvm/test/CodeGen/X86/sdiv-exact.ll +++ b/llvm/test/CodeGen/X86/sdiv-exact.ll @@ -3,7 +3,7 @@ define i32 @test1(i32 %x) { %div = sdiv exact i32 %x, 25 ret i32 %div -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: imull $-1030792151, 4(%esp) ; CHECK-NEXT: ret } @@ -11,7 +11,7 @@ define i32 @test1(i32 %x) { define i32 @test2(i32 %x) { %div = sdiv exact i32 %x, 24 ret i32 %div -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: sarl $3 ; CHECK-NEXT: imull $-1431655765 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll index d68b00b69a2..c2aa61714a7 100644 --- a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll +++ b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll @@ -20,7 +20,7 @@ false: %retvalue = call i32 @test_basic(i32 %newlen) ret i32 %retvalue -; X32: test_basic: +; X32-LABEL: test_basic: ; X32: cmpl %gs:48, %esp ; X32-NEXT: ja .LBB0_2 @@ -41,7 +41,7 @@ false: ; X32-NEXT: calll __morestack_allocate_stack_space ; X32-NEXT: addl $16, %esp -; X64: test_basic: +; X64-LABEL: test_basic: ; X64: cmpq %fs:112, %rsp ; X64-NEXT: ja .LBB0_2 diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll index 09ca07b31a1..55da76907bd 100644 --- a/llvm/test/CodeGen/X86/select.ll +++ b/llvm/test/CodeGen/X86/select.ll @@ -10,11 +10,11 @@ define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind { %t4 = select i1 %r, %0 %t0, %0 %t1 %t5 = extractvalue %0 %t4, 1 ret i32 %t5 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: cmovneq %rdi, %rsi ; CHECK: movl (%rsi), %eax -; ATOM: test1: +; ATOM-LABEL: test1: ; ATOM: cmovneq %rdi, %rsi ; ATOM: movl (%rsi), %eax } @@ -33,11 +33,11 @@ bb90: ; preds = %bb84, %bb72 unreachable bb91: ; preds = %bb84 ret i32 0 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movnew ; CHECK: movswl -; ATOM: test2: +; ATOM-LABEL: test2: ; ATOM: movnew ; ATOM: movswl } @@ -51,10 +51,10 @@ entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] %iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01 ; <float> [#uses=1] ret float %iftmp.0.0 -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movss {{.*}},4), %xmm0 -; ATOM: test3: +; ATOM-LABEL: test3: ; ATOM: movss {{.*}},4), %xmm0 } @@ -65,10 +65,10 @@ entry: %1 = getelementptr i8* %P, i32 %iftmp.0.0 ; <i8*> [#uses=1] %2 = load i8* %1, align 1 ; <i8> [#uses=1] ret i8 %2 -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movsbl ({{.*}},4), %eax -; ATOM: test4: +; ATOM-LABEL: test4: ; ATOM: movsbl ({{.*}},4), %eax } @@ -76,9 +76,9 @@ define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind { %x = select i1 %c, <2 x i16> %a, <2 x i16> %b store <2 x i16> %x, <2 x i16>* %p ret void -; CHECK: test5: +; CHECK-LABEL: test5: -; ATOM: test5: +; ATOM-LABEL: test5: } define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind { @@ -91,13 +91,13 @@ define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind { ret void ; Verify that the fmul gets sunk into the one part of the diamond where it is ; needed. -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: je ; CHECK: ret ; CHECK: mulps ; CHECK: ret -; ATOM: test6: +; ATOM-LABEL: test6: ; ATOM: je ; ATOM: ret ; ATOM: mulps @@ -109,11 +109,11 @@ define x86_fp80 @test7(i32 %tmp8) nounwind { %tmp9 = icmp sgt i32 %tmp8, -1 ; <i1> [#uses=1] %retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000 ret x86_fp80 %retval -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: leaq ; CHECK: fldt (%r{{.}}x,%r{{.}}x) -; ATOM: test7: +; ATOM-LABEL: test7: ; ATOM: leaq ; ATOM: fldt (%r{{.}}x,%r{{.}}x) } @@ -125,9 +125,9 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) store <6 x i32> %val, <6 x i32>* %dst.addr ret void -; CHECK: test8: +; CHECK-LABEL: test8: -; ATOM: test8: +; ATOM-LABEL: test8: } @@ -137,13 +137,13 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone { %cmp = icmp ne i64 %x, 0 %cond = select i1 %cmp, i64 %y, i64 -1 ret i64 %cond -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: cmpq $1, %rdi ; CHECK: sbbq %rax, %rax ; CHECK: orq %rsi, %rax ; CHECK: ret -; ATOM: test9: +; ATOM-LABEL: test9: ; ATOM: cmpq $1, %rdi ; ATOM: sbbq %rax, %rax ; ATOM: orq %rsi, %rax @@ -155,13 +155,13 @@ define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone { %cmp = icmp eq i64 %x, 0 %cond = select i1 %cmp, i64 -1, i64 %y ret i64 %cond -; CHECK: test9a: +; CHECK-LABEL: test9a: ; CHECK: cmpq $1, %rdi ; CHECK: sbbq %rax, %rax ; CHECK: orq %rsi, %rax ; CHECK: ret -; ATOM: test9a: +; ATOM-LABEL: test9a: ; ATOM: cmpq $1, %rdi ; ATOM: sbbq %rax, %rax ; ATOM: orq %rsi, %rax @@ -173,13 +173,13 @@ define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone { %A = sext i1 %cmp to i64 %cond = or i64 %y, %A ret i64 %cond -; CHECK: test9b: +; CHECK-LABEL: test9b: ; CHECK: cmpq $1, %rdi ; CHECK: sbbq %rax, %rax ; CHECK: orq %rsi, %rax ; CHECK: ret -; ATOM: test9b: +; ATOM-LABEL: test9b: ; ATOM: cmpq $1, %rdi ; ATOM: sbbq %rax, %rax ; ATOM: orq %rsi, %rax @@ -191,13 +191,13 @@ define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone { %cmp = icmp eq i64 %x, 0 %cond = select i1 %cmp, i64 -1, i64 1 ret i64 %cond -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: cmpq $1, %rdi ; CHECK: sbbq %rax, %rax ; CHECK: orq $1, %rax ; CHECK: ret -; ATOM: test10: +; ATOM-LABEL: test10: ; ATOM: cmpq $1, %rdi ; ATOM: sbbq %rax, %rax ; ATOM: orq $1, %rax @@ -210,14 +210,14 @@ define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone { %cmp = icmp eq i64 %x, 0 %cond = select i1 %cmp, i64 %y, i64 -1 ret i64 %cond -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: cmpq $1, %rdi ; CHECK: sbbq %rax, %rax ; CHECK: notq %rax ; CHECK: orq %rsi, %rax ; CHECK: ret -; ATOM: test11: +; ATOM-LABEL: test11: ; ATOM: cmpq $1, %rdi ; ATOM: sbbq %rax, %rax ; ATOM: notq %rax @@ -229,14 +229,14 @@ define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone { %cmp = icmp ne i64 %x, 0 %cond = select i1 %cmp, i64 -1, i64 %y ret i64 %cond -; CHECK: test11a: +; CHECK-LABEL: test11a: ; CHECK: cmpq $1, %rdi ; CHECK: sbbq %rax, %rax ; CHECK: notq %rax ; CHECK: orq %rsi, %rax ; CHECK: ret -; ATOM: test11a: +; ATOM-LABEL: test11a: ; ATOM: cmpq $1, %rdi ; ATOM: sbbq %rax, %rax ; ATOM: notq %rax @@ -255,13 +255,13 @@ entry: %D = select i1 %B, i64 -1, i64 %C %call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone ret i8* %call -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: movq $-1, %rdi ; CHECK: mulq ; CHECK: cmovnoq %rax, %rdi ; CHECK: jmp __Znam -; ATOM: test12: +; ATOM-LABEL: test12: ; ATOM: mulq ; ATOM: movq $-1, %rdi ; ATOM: cmovnoq %rax, %rdi @@ -274,12 +274,12 @@ define i32 @test13(i32 %a, i32 %b) nounwind { %c = icmp ult i32 %a, %b %d = sext i1 %c to i32 ret i32 %d -; CHECK: test13: +; CHECK-LABEL: test13: ; CHECK: cmpl ; CHECK-NEXT: sbbl ; CHECK-NEXT: ret -; ATOM: test13: +; ATOM-LABEL: test13: ; ATOM: cmpl ; ATOM-NEXT: sbbl ; ATOM: ret @@ -289,13 +289,13 @@ define i32 @test14(i32 %a, i32 %b) nounwind { %c = icmp uge i32 %a, %b %d = sext i1 %c to i32 ret i32 %d -; CHECK: test14: +; CHECK-LABEL: test14: ; CHECK: cmpl ; CHECK-NEXT: sbbl ; CHECK-NEXT: notl ; CHECK-NEXT: ret -; ATOM: test14: +; ATOM-LABEL: test14: ; ATOM: cmpl ; ATOM-NEXT: sbbl ; ATOM-NEXT: notl @@ -308,11 +308,11 @@ entry: %cmp = icmp ne i32 %x, 0 %sub = sext i1 %cmp to i32 ret i32 %sub -; CHECK: test15: +; CHECK-LABEL: test15: ; CHECK: negl ; CHECK: sbbl -; ATOM: test15: +; ATOM-LABEL: test15: ; ATOM: negl ; ATOM: sbbl } @@ -322,11 +322,11 @@ entry: %cmp = icmp ne i64 %x, 0 %conv1 = sext i1 %cmp to i64 ret i64 %conv1 -; CHECK: test16: +; CHECK-LABEL: test16: ; CHECK: negq ; CHECK: sbbq -; ATOM: test16: +; ATOM-LABEL: test16: ; ATOM: negq ; ATOM: sbbq } @@ -336,11 +336,11 @@ entry: %cmp = icmp ne i16 %x, 0 %sub = sext i1 %cmp to i16 ret i16 %sub -; CHECK: test17: +; CHECK-LABEL: test17: ; CHECK: negw ; CHECK: sbbw -; ATOM: test17: +; ATOM-LABEL: test17: ; ATOM: negw ; ATOM: sbbw } @@ -349,11 +349,11 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind { %cmp = icmp slt i32 %x, 15 %sel = select i1 %cmp, i8 %a, i8 %b ret i8 %sel -; CHECK: test18: +; CHECK-LABEL: test18: ; CHECK: cmpl $15, %edi ; CHECK: cmovgel %edx -; ATOM: test18: +; ATOM-LABEL: test18: ; ATOM: cmpl $15, %edi ; ATOM: cmovgel %edx } diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll index 5b2409d2396..a6c2377e036 100644 --- a/llvm/test/CodeGen/X86/select_const.ll +++ b/llvm/test/CodeGen/X86/select_const.ll @@ -7,7 +7,7 @@ entry: %retval.0 = select i1 %cmp, i64 2, i64 %add ret i64 %retval.0 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: leaq 1(%rdi), %rax ; CHECK: cmpq $2, %rdi ; CHECK: cmoveq %rdi, %rax diff --git a/llvm/test/CodeGen/X86/sext-load.ll b/llvm/test/CodeGen/X86/sext-load.ll index 58c93229a2c..2753e876629 100644 --- a/llvm/test/CodeGen/X86/sext-load.ll +++ b/llvm/test/CodeGen/X86/sext-load.ll @@ -3,7 +3,7 @@ ; When doing sign extension, use the sext-load lowering to take advantage of ; x86's sign extension during loads. ; -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movsbl {{.*}}, %eax ; CHECK-NEXT: ret define i32 @test1(i32 %X) nounwind { @@ -16,7 +16,7 @@ entry: ; When using a sextload representation, ensure that the sign extension is ; preserved even when removing shifted-out low bits. ; -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movswl {{.*}}, %eax ; CHECK-NEXT: ret define i32 @test2({i16, [6 x i8]}* %this) { diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll index 51f83036c23..113dedb4a00 100644 --- a/llvm/test/CodeGen/X86/shift-combine.ll +++ b/llvm/test/CodeGen/X86/shift-combine.ll @@ -3,7 +3,7 @@ @array = weak global [4 x i32] zeroinitializer define i32 @test_lshr_and(i32 %x) { -; CHECK: test_lshr_and: +; CHECK-LABEL: test_lshr_and: ; CHECK-NOT: shrl ; CHECK: andl $12, ; CHECK: movl {{.*}}array{{.*}}, diff --git a/llvm/test/CodeGen/X86/shift-folding.ll b/llvm/test/CodeGen/X86/shift-folding.ll index c518cdd3aa4..ea9002c397b 100644 --- a/llvm/test/CodeGen/X86/shift-folding.ll +++ b/llvm/test/CodeGen/X86/shift-folding.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -verify-coalescing | FileCheck %s define i32* @test1(i32* %P, i32 %X) { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: shrl ; CHECK-NOT: shll ; CHECK: ret @@ -14,7 +14,7 @@ entry: } define i32* @test2(i32* %P, i32 %X) { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: shll $4 ; CHECK-NOT: shll ; CHECK: ret @@ -27,7 +27,7 @@ entry: } define i32* @test3(i32* %P, i32 %X) { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK-NOT: shrl ; CHECK-NOT: shll ; CHECK: ret @@ -39,7 +39,7 @@ entry: } define fastcc i32 @test4(i32* %d) { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK-NOT: shrl ; CHECK: ret @@ -52,7 +52,7 @@ entry: define i64 @test5(i16 %i, i32* %arr) { ; Ensure that we don't fold away shifts which have multiple uses, as they are ; just re-introduced for the second use. -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK-NOT: shrl ; CHECK: shrl $11 ; CHECK-NOT: shrl diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll index 30a5b6207db..bb892011e2d 100644 --- a/llvm/test/CodeGen/X86/shrink-compare.ll +++ b/llvm/test/CodeGen/X86/shrink-compare.ll @@ -15,7 +15,7 @@ if.then: if.end: ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: cmpb $47, (%{{rdi|rcx}}) } @@ -31,7 +31,7 @@ if.then: if.end: ret void -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: cmpb $47, %{{dil|cl}} } @@ -47,7 +47,7 @@ if.then: if.end: ret void -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmpb $-1, %{{dil|cl}} } @@ -85,7 +85,7 @@ if.then: if.end: ret void -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK-NOT: cmpl $1,{{.*}}x+4 ; CHECK: ret } diff --git a/llvm/test/CodeGen/X86/sibcall-6.ll b/llvm/test/CodeGen/X86/sibcall-6.ll index 2cdc3c4ec77..c9dff6b73d2 100644 --- a/llvm/test/CodeGen/X86/sibcall-6.ll +++ b/llvm/test/CodeGen/X86/sibcall-6.ll @@ -6,7 +6,7 @@ target triple = "i386-unknown-linux-gnu" declare void @callee1(i32 inreg, i32 inreg, i32 inreg) define void @test1(i32 %a, i32 %b) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: calll callee1@PLT tail call void @callee1(i32 inreg 0, i32 inreg 0, i32 inreg 0) nounwind ret void diff --git a/llvm/test/CodeGen/X86/sincos-opt.ll b/llvm/test/CodeGen/X86/sincos-opt.ll index f800c5861d9..2dc8816f840 100644 --- a/llvm/test/CodeGen/X86/sincos-opt.ll +++ b/llvm/test/CodeGen/X86/sincos-opt.ll @@ -8,12 +8,12 @@ define float @test1(float %x) nounwind { entry: -; GNU_SINCOS: test1: +; GNU_SINCOS-LABEL: test1: ; GNU_SINCOS: callq sincosf ; GNU_SINCOS: movss 4(%rsp), %xmm0 ; GNU_SINCOS: addss (%rsp), %xmm0 -; OSX_SINCOS: test1: +; OSX_SINCOS-LABEL: test1: ; OSX_SINCOS: callq ___sincosf_stret ; OSX_SINCOS: pshufd $1, %xmm0, %xmm1 ; OSX_SINCOS: addss %xmm0, %xmm1 @@ -29,12 +29,12 @@ entry: define double @test2(double %x) nounwind { entry: -; GNU_SINCOS: test2: +; GNU_SINCOS-LABEL: test2: ; GNU_SINCOS: callq sincos ; GNU_SINCOS: movsd 16(%rsp), %xmm0 ; GNU_SINCOS: addsd 8(%rsp), %xmm0 -; OSX_SINCOS: test2: +; OSX_SINCOS-LABEL: test2: ; OSX_SINCOS: callq ___sincos_stret ; OSX_SINCOS: addsd %xmm1, %xmm0 @@ -49,7 +49,7 @@ entry: define x86_fp80 @test3(x86_fp80 %x) nounwind { entry: -; GNU_SINCOS: test3: +; GNU_SINCOS-LABEL: test3: ; GNU_SINCOS: callq sinl ; GNU_SINCOS: callq cosl ; GNU_SINCOS: ret diff --git a/llvm/test/CodeGen/X86/sincos.ll b/llvm/test/CodeGen/X86/sincos.ll index 734f48ae329..8f0e6f1edf6 100644 --- a/llvm/test/CodeGen/X86/sincos.ll +++ b/llvm/test/CodeGen/X86/sincos.ll @@ -9,7 +9,7 @@ declare double @sin(double) readonly declare x86_fp80 @sinl(x86_fp80) readonly -; SIN: test1: +; SIN-LABEL: test1: define float @test1(float %X) { %Y = call float @sinf(float %X) readonly ret float %Y @@ -21,7 +21,7 @@ define float @test1(float %X) { ; SAFE: test1 ; SAFE-NOT: fsin -; SIN: test2: +; SIN-LABEL: test2: define double @test2(double %X) { %Y = call double @sin(double %X) readonly ret double %Y @@ -33,7 +33,7 @@ define double @test2(double %X) { ; SAFE: test2 ; SAFE-NOT: fsin -; SIN: test3: +; SIN-LABEL: test3: define x86_fp80 @test3(x86_fp80 %X) { %Y = call x86_fp80 @sinl(x86_fp80 %X) readonly ret x86_fp80 %Y @@ -49,8 +49,8 @@ declare double @cos(double) readonly declare x86_fp80 @cosl(x86_fp80) readonly -; SIN: test4: -; COS: test3: +; SIN-LABEL: test4: +; COS-LABEL: test3: define float @test4(float %X) { %Y = call float @cosf(float %X) readonly ret float %Y diff --git a/llvm/test/CodeGen/X86/smul-with-overflow.ll b/llvm/test/CodeGen/X86/smul-with-overflow.ll index 2d0b2f7aa91..cefbda64751 100644 --- a/llvm/test/CodeGen/X86/smul-with-overflow.ll +++ b/llvm/test/CodeGen/X86/smul-with-overflow.ll @@ -17,7 +17,7 @@ normal: overflow: %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind ret i1 false -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: imull ; CHECK-NEXT: jno } @@ -36,7 +36,7 @@ overflow: normal: %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind ret i1 true -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: imull ; CHECK-NEXT: jno } @@ -50,7 +50,7 @@ entry: %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2) %tmp2 = extractvalue { i32, i1 } %tmp1, 0 ret i32 %tmp2 -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: addl ; CHECK-NEXT: addl ; CHECK-NEXT: ret @@ -62,7 +62,7 @@ entry: %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4) %tmp2 = extractvalue { i32, i1 } %tmp1, 0 ret i32 %tmp2 -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: addl ; CHECK: mull ; CHECK-NEXT: ret @@ -78,6 +78,6 @@ entry: ret i1 %overflow ; Was returning false, should return true (not constant folded yet though). ; PR13991 -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK-NOT: xorb } diff --git a/llvm/test/CodeGen/X86/sse1.ll b/llvm/test/CodeGen/X86/sse1.ll index 9b2e05b5bed..47c6429b181 100644 --- a/llvm/test/CodeGen/X86/sse1.ll +++ b/llvm/test/CodeGen/X86/sse1.ll @@ -33,7 +33,7 @@ entry: %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0 %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1 ret <2 x float> %tmp9 -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK-NOT: shufps $16 ; CHECK: shufps $1, ; CHECK-NOT: shufps $16 diff --git a/llvm/test/CodeGen/X86/sse2-mul.ll b/llvm/test/CodeGen/X86/sse2-mul.ll index 0466d60ec30..e066368dc73 100644 --- a/llvm/test/CodeGen/X86/sse2-mul.ll +++ b/llvm/test/CodeGen/X86/sse2-mul.ll @@ -3,7 +3,7 @@ define <4 x i32> @test1(<4 x i32> %x, <4 x i32> %y) { %m = mul <4 x i32> %x, %y ret <4 x i32> %m -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: pshufd $49 ; CHECK: pmuludq ; CHECK: pshufd $49 diff --git a/llvm/test/CodeGen/X86/sse2-vector-shifts.ll b/llvm/test/CodeGen/X86/sse2-vector-shifts.ll index 312ca9533cc..e2d612567a1 100644 --- a/llvm/test/CodeGen/X86/sse2-vector-shifts.ll +++ b/llvm/test/CodeGen/X86/sse2-vector-shifts.ll @@ -8,7 +8,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_sllw_1: +; CHECK-LABEL: test_sllw_1: ; CHECK: psllw $0, %xmm0 ; CHECK-NEXT: ret @@ -18,7 +18,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_sllw_2: +; CHECK-LABEL: test_sllw_2: ; CHECK: paddw %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -28,7 +28,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_sllw_3: +; CHECK-LABEL: test_sllw_3: ; CHECK: xorps %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -38,7 +38,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_slld_1: +; CHECK-LABEL: test_slld_1: ; CHECK: pslld $0, %xmm0 ; CHECK-NEXT: ret @@ -48,7 +48,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_slld_2: +; CHECK-LABEL: test_slld_2: ; CHECK: paddd %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -58,7 +58,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_slld_3: +; CHECK-LABEL: test_slld_3: ; CHECK: xorps %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -68,7 +68,7 @@ entry: ret <2 x i64> %shl } -; CHECK: test_sllq_1: +; CHECK-LABEL: test_sllq_1: ; CHECK: psllq $0, %xmm0 ; CHECK-NEXT: ret @@ -78,7 +78,7 @@ entry: ret <2 x i64> %shl } -; CHECK: test_sllq_2: +; CHECK-LABEL: test_sllq_2: ; CHECK: paddq %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -88,7 +88,7 @@ entry: ret <2 x i64> %shl } -; CHECK: test_sllq_3: +; CHECK-LABEL: test_sllq_3: ; CHECK: xorps %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -100,7 +100,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_sraw_1: +; CHECK-LABEL: test_sraw_1: ; CHECK: psraw $0, %xmm0 ; CHECK-NEXT: ret @@ -110,7 +110,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_sraw_2: +; CHECK-LABEL: test_sraw_2: ; CHECK: psraw $1, %xmm0 ; CHECK-NEXT: ret @@ -120,7 +120,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_sraw_3: +; CHECK-LABEL: test_sraw_3: ; CHECK: psraw $16, %xmm0 ; CHECK-NEXT: ret @@ -130,7 +130,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_srad_1: +; CHECK-LABEL: test_srad_1: ; CHECK: psrad $0, %xmm0 ; CHECK-NEXT: ret @@ -140,7 +140,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_srad_2: +; CHECK-LABEL: test_srad_2: ; CHECK: psrad $1, %xmm0 ; CHECK-NEXT: ret @@ -150,7 +150,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_srad_3: +; CHECK-LABEL: test_srad_3: ; CHECK: psrad $32, %xmm0 ; CHECK-NEXT: ret @@ -162,7 +162,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_srlw_1: +; CHECK-LABEL: test_srlw_1: ; CHECK: psrlw $0, %xmm0 ; CHECK-NEXT: ret @@ -172,7 +172,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_srlw_2: +; CHECK-LABEL: test_srlw_2: ; CHECK: psrlw $1, %xmm0 ; CHECK-NEXT: ret @@ -182,7 +182,7 @@ entry: ret <8 x i16> %shl } -; CHECK: test_srlw_3: +; CHECK-LABEL: test_srlw_3: ; CHECK: xorps %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -192,7 +192,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_srld_1: +; CHECK-LABEL: test_srld_1: ; CHECK: psrld $0, %xmm0 ; CHECK-NEXT: ret @@ -202,7 +202,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_srld_2: +; CHECK-LABEL: test_srld_2: ; CHECK: psrld $1, %xmm0 ; CHECK-NEXT: ret @@ -212,7 +212,7 @@ entry: ret <4 x i32> %shl } -; CHECK: test_srld_3: +; CHECK-LABEL: test_srld_3: ; CHECK: xorps %xmm0, %xmm0 ; CHECK-NEXT: ret @@ -222,7 +222,7 @@ entry: ret <2 x i64> %shl } -; CHECK: test_srlq_1: +; CHECK-LABEL: test_srlq_1: ; CHECK: psrlq $0, %xmm0 ; CHECK-NEXT: ret @@ -232,7 +232,7 @@ entry: ret <2 x i64> %shl } -; CHECK: test_srlq_2: +; CHECK-LABEL: test_srlq_2: ; CHECK: psrlq $1, %xmm0 ; CHECK-NEXT: ret @@ -242,6 +242,6 @@ entry: ret <2 x i64> %shl } -; CHECK: test_srlq_3: +; CHECK-LABEL: test_srlq_3: ; CHECK: xorps %xmm0, %xmm0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/X86/sse2.ll b/llvm/test/CodeGen/X86/sse2.ll index 36a0fd91bd8..217139a2b75 100644 --- a/llvm/test/CodeGen/X86/sse2.ll +++ b/llvm/test/CodeGen/X86/sse2.ll @@ -8,7 +8,7 @@ define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { store <2 x double> %tmp9, <2 x double>* %r, align 16 ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movl 8(%esp), %eax ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movlpd 12(%esp), %xmm0 @@ -24,7 +24,7 @@ define void @test2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { store <2 x double> %tmp9, <2 x double>* %r, align 16 ret void -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl 8(%esp), %eax ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movhpd 12(%esp), %xmm0 @@ -60,7 +60,7 @@ define void @test4(<4 x float> %X, <4 x float>* %res) nounwind { } define <4 x i32> @test5(i8** %ptr) nounwind { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: pxor ; CHECK: punpcklbw ; CHECK: punpcklwd @@ -86,7 +86,7 @@ define void @test6(<4 x float>* %res, <4 x float>* %A) nounwind { store <4 x float> %tmp2, <4 x float>* %res ret void -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: movaps (%eax), %xmm0 ; CHECK: movaps %xmm0, (%eax) } @@ -97,7 +97,7 @@ define void @test7() nounwind { store <4 x float> %2, <4 x float>* null ret void -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: xorps %xmm0, %xmm0 ; CHECK: movaps %xmm0, 0 } @@ -115,7 +115,7 @@ define <2 x i64> @test8() nounwind { %tmp15 = insertelement <4 x i32> %tmp14, i32 %tmp7, i32 3 ; <<4 x i32>> [#uses=1] %tmp16 = bitcast <4 x i32> %tmp15 to <2 x i64> ; <<2 x i64>> [#uses=1] ret <2 x i64> %tmp16 -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: movups (%eax), %xmm0 } @@ -125,7 +125,7 @@ define <4 x float> @test9(i32 %dummy, float %a, float %b, float %c, float %d) no %tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1] %tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1] ret <4 x float> %tmp13 -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: movups 8(%esp), %xmm0 } @@ -135,7 +135,7 @@ define <4 x float> @test10(float %a, float %b, float %c, float %d) nounwind { %tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1] %tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1] ret <4 x float> %tmp13 -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: movaps 4(%esp), %xmm0 } @@ -143,7 +143,7 @@ define <2 x double> @test11(double %a, double %b) nounwind { %tmp = insertelement <2 x double> undef, double %a, i32 0 ; <<2 x double>> [#uses=1] %tmp7 = insertelement <2 x double> %tmp, double %b, i32 1 ; <<2 x double>> [#uses=1] ret <2 x double> %tmp7 -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: movaps 4(%esp), %xmm0 } @@ -154,7 +154,7 @@ define void @test12() nounwind { %tmp4 = fadd <4 x float> %tmp2, %tmp3 ; <<4 x float>> [#uses=1] store <4 x float> %tmp4, <4 x float>* null ret void -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: movhlps ; CHECK: shufps } @@ -177,7 +177,7 @@ define <4 x float> @test14(<4 x float>* %x, <4 x float>* %y) nounwind { %tmp21 = fsub <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1] %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x float>> [#uses=1] ret <4 x float> %tmp27 -; CHECK: test14: +; CHECK-LABEL: test14: ; CHECK: subps [[X1:%xmm[0-9]+]], [[X2:%xmm[0-9]+]] ; CHECK: addps [[X1]], [[X0:%xmm[0-9]+]] ; CHECK: movlhps [[X2]], [[X0]] @@ -189,12 +189,12 @@ entry: %tmp3 = load <4 x float>* %x ; <<4 x float>> [#uses=1] %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1] ret <4 x float> %tmp4 -; CHECK: test15: +; CHECK-LABEL: test15: ; CHECK: movhlps %xmm1, %xmm0 } ; PR8900 -; CHECK: test16: +; CHECK-LABEL: test16: ; CHECK: unpcklpd ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/sse4a.ll b/llvm/test/CodeGen/X86/sse4a.ll index 076e2133649..165d47639d7 100644 --- a/llvm/test/CodeGen/X86/sse4a.ll +++ b/llvm/test/CodeGen/X86/sse4a.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movntss tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind ret void @@ -10,7 +10,7 @@ define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp { declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>) define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movntsd tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind ret void @@ -19,7 +19,7 @@ define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp { declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>) define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: extrq %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) ret <2 x i64> %1 @@ -28,7 +28,7 @@ define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp { declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: extrq %1 = bitcast <2 x i64> %y to <16 x i8> %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind @@ -38,7 +38,7 @@ define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: insertq %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6) ret <2 x i64> %1 @@ -47,7 +47,7 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: insertq %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind ret <2 x i64> %1 diff --git a/llvm/test/CodeGen/X86/stack-align-memcpy.ll b/llvm/test/CodeGen/X86/stack-align-memcpy.ll index 74945e5bb1b..87bb85fad83 100644 --- a/llvm/test/CodeGen/X86/stack-align-memcpy.ll +++ b/llvm/test/CodeGen/X86/stack-align-memcpy.ll @@ -9,7 +9,7 @@ define void @test1(%struct.foo* nocapture %x, i32 %y) nounwind { call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x) ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: andl $-16, %esp ; CHECK: movl %esp, %esi ; CHECK-NOT: rep;movsl diff --git a/llvm/test/CodeGen/X86/stack-align.ll b/llvm/test/CodeGen/X86/stack-align.ll index 0ddb2378ef2..2918a68a9a0 100644 --- a/llvm/test/CodeGen/X86/stack-align.ll +++ b/llvm/test/CodeGen/X86/stack-align.ll @@ -45,7 +45,7 @@ entry: %0 = ptrtoint [2048 x i8]* %buffer to i32 %and = and i32 %0, -16 ret i32 %and -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK-NOT: and ; CHECK: ret } diff --git a/llvm/test/CodeGen/X86/store-narrow.ll b/llvm/test/CodeGen/X86/store-narrow.ll index 0dd228eb145..fab266f7caf 100644 --- a/llvm/test/CodeGen/X86/store-narrow.ll +++ b/llvm/test/CodeGen/X86/store-narrow.ll @@ -13,10 +13,10 @@ entry: store i32 %D, i32* %a0, align 4 ret void -; X64: test1: +; X64-LABEL: test1: ; X64: movb %sil, (%rdi) -; X32: test1: +; X32-LABEL: test1: ; X32: movb 8(%esp), %al ; X32: movb %al, (%{{.*}}) } @@ -30,10 +30,10 @@ entry: %D = or i32 %B, %CS store i32 %D, i32* %a0, align 4 ret void -; X64: test2: +; X64-LABEL: test2: ; X64: movb %sil, 1(%rdi) -; X32: test2: +; X32-LABEL: test2: ; X32: movb 8(%esp), %al ; X32: movb %al, 1(%{{.*}}) } @@ -46,10 +46,10 @@ entry: %D = or i32 %B, %C store i32 %D, i32* %a0, align 4 ret void -; X64: test3: +; X64-LABEL: test3: ; X64: movw %si, (%rdi) -; X32: test3: +; X32-LABEL: test3: ; X32: movw 8(%esp), %ax ; X32: movw %ax, (%{{.*}}) } @@ -63,10 +63,10 @@ entry: %D = or i32 %B, %CS store i32 %D, i32* %a0, align 4 ret void -; X64: test4: +; X64-LABEL: test4: ; X64: movw %si, 2(%rdi) -; X32: test4: +; X32-LABEL: test4: ; X32: movl 8(%esp), %eax ; X32: movw %ax, 2(%{{.*}}) } @@ -80,10 +80,10 @@ entry: %D = or i64 %B, %CS store i64 %D, i64* %a0, align 4 ret void -; X64: test5: +; X64-LABEL: test5: ; X64: movw %si, 2(%rdi) -; X32: test5: +; X32-LABEL: test5: ; X32: movzwl 8(%esp), %eax ; X32: movw %ax, 2(%{{.*}}) } @@ -97,11 +97,11 @@ entry: %D = or i64 %B, %CS store i64 %D, i64* %a0, align 4 ret void -; X64: test6: +; X64-LABEL: test6: ; X64: movb %sil, 5(%rdi) -; X32: test6: +; X32-LABEL: test6: ; X32: movb 8(%esp), %al ; X32: movb %al, 5(%{{.*}}) } @@ -116,11 +116,11 @@ entry: %D = or i64 %B, %CS store i64 %D, i64* %a0, align 4 ret i32 %OtherLoad -; X64: test7: +; X64-LABEL: test7: ; X64: movb %sil, 5(%rdi) -; X32: test7: +; X32-LABEL: test7: ; X32: movb 8(%esp), %cl ; X32: movb %cl, 5(%{{.*}}) } @@ -129,7 +129,7 @@ entry: @g_16 = internal global i32 -1 -; X64: test8: +; X64-LABEL: test8: ; X64-NEXT: movl _g_16(%rip), %eax ; X64-NEXT: movl $0, _g_16(%rip) ; X64-NEXT: orl $1, %eax @@ -143,7 +143,7 @@ define void @test8() nounwind { ret void } -; X64: test9: +; X64-LABEL: test9: ; X64-NEXT: orb $1, _g_16(%rip) ; X64-NEXT: ret define void @test9() nounwind { @@ -154,7 +154,7 @@ define void @test9() nounwind { } ; rdar://8494845 + PR8244 -; X64: test10: +; X64-LABEL: test10: ; X64-NEXT: movsbl (%rdi), %eax ; X64-NEXT: shrl $8, %eax ; X64-NEXT: ret diff --git a/llvm/test/CodeGen/X86/store_op_load_fold.ll b/llvm/test/CodeGen/X86/store_op_load_fold.ll index 070cccdb87d..41b0a9c26f5 100644 --- a/llvm/test/CodeGen/X86/store_op_load_fold.ll +++ b/llvm/test/CodeGen/X86/store_op_load_fold.ll @@ -19,7 +19,7 @@ define void @foo() nounwind { %struct.S2 = type { i64, i16, [2 x i8], i8, [3 x i8], [7 x i8], i8, [8 x i8] } @s2 = external global %struct.S2, align 16 define void @test2() nounwind uwtable ssp { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: mov ; CHECK-NEXT: and ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/X86/sub.ll b/llvm/test/CodeGen/X86/sub.ll index ee5ea1d0fb6..3cf79a3deca 100644 --- a/llvm/test/CodeGen/X86/sub.ll +++ b/llvm/test/CodeGen/X86/sub.ll @@ -4,7 +4,7 @@ define i32 @test1(i32 %x) { %xor = xor i32 %x, 31 %sub = sub i32 32, %xor ret i32 %sub -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: xorl $-32 ; CHECK-NEXT: addl $33 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/X86/switch-bt.ll b/llvm/test/CodeGen/X86/switch-bt.ll index 58a5c033854..a80002bc97c 100644 --- a/llvm/test/CodeGen/X86/switch-bt.ll +++ b/llvm/test/CodeGen/X86/switch-bt.ll @@ -53,7 +53,7 @@ declare void @foo(i32) ; Don't zero extend the test operands to pointer type if it can be avoided. ; rdar://8781238 define void @test2(i32 %x) nounwind ssp { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: cmpl $6 ; CHECK: ja @@ -81,7 +81,7 @@ if.end: ; preds = %entry declare void @bar() define void @test3(i32 %x) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: cmpl $5 ; CHECK: ja ; CHECK: cmpl $4 diff --git a/llvm/test/CodeGen/X86/switch-order-weight.ll b/llvm/test/CodeGen/X86/switch-order-weight.ll index 0fdd56d4e1d..207e0b3f707 100644 --- a/llvm/test/CodeGen/X86/switch-order-weight.ll +++ b/llvm/test/CodeGen/X86/switch-order-weight.ll @@ -10,7 +10,7 @@ entry: i32 20, label %if.then5 ] -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: unr ; CHECK: cmpl $10 ; CHECK: bar diff --git a/llvm/test/CodeGen/X86/tail-call-got.ll b/llvm/test/CodeGen/X86/tail-call-got.ll index 1d7eb2e2987..84d561dcd8c 100644 --- a/llvm/test/CodeGen/X86/tail-call-got.ll +++ b/llvm/test/CodeGen/X86/tail-call-got.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 target triple = "i386-unknown-freebsd9.0" define double @test1(double %x) nounwind readnone { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movl foo@GOT ; CHECK-NEXT: jmpl %1 = tail call double @foo(double %x) nounwind readnone @@ -14,7 +14,7 @@ define double @test1(double %x) nounwind readnone { declare double @foo(double) readnone define double @test2(double %x) nounwind readnone { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movl sin@GOT ; CHECK-NEXT: jmpl %1 = tail call double @sin(double %x) nounwind readnone diff --git a/llvm/test/CodeGen/X86/tailcall-disable.ll b/llvm/test/CodeGen/X86/tailcall-disable.ll index b628f5e537f..1fd2d72dc57 100644 --- a/llvm/test/CodeGen/X86/tailcall-disable.ll +++ b/llvm/test/CodeGen/X86/tailcall-disable.ll @@ -15,12 +15,12 @@ entry: ret i32 %call } -; CALL: test1: +; CALL-LABEL: test1: ; CALL-NOT: ret ; CALL: callq helper ; CALL: ret -; JMP: test1: +; JMP-LABEL: test1: ; JMP-NOT: ret ; JMP: jmp helper # TAILCALL @@ -30,11 +30,11 @@ entry: ret i32 %call } -; CALL: test2: +; CALL-LABEL: test2: ; CALL-NOT: ret ; CALL: callq test2 ; CALL: ret -; JMP: test2: +; JMP-LABEL: test2: ; JMP-NOT: ret ; JMP: jmp test2 # TAILCALL diff --git a/llvm/test/CodeGen/X86/testl-commute.ll b/llvm/test/CodeGen/X86/testl-commute.ll index 0e6f6363cb8..bf6debf1754 100644 --- a/llvm/test/CodeGen/X86/testl-commute.ll +++ b/llvm/test/CodeGen/X86/testl-commute.ll @@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin7" define i32 @test(i32* %P, i32* %G) nounwind { -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: ret ; CHECK: testl (%{{.*}}), %{{.*}} ; CHECK: ret @@ -28,7 +28,7 @@ bb1: ; preds = %entry } define i32 @test2(i32* %P, i32* %G) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK-NOT: ret ; CHECK: testl (%{{.*}}), %{{.*}} ; CHECK: ret @@ -49,7 +49,7 @@ bb1: ; preds = %entry } define i32 @test3(i32* %P, i32* %G) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK-NOT: ret ; CHECK: testl (%{{.*}}), %{{.*}} ; CHECK: ret diff --git a/llvm/test/CodeGen/X86/tlv-1.ll b/llvm/test/CodeGen/X86/tlv-1.ll index 92dac309662..f9700114a88 100644 --- a/llvm/test/CodeGen/X86/tlv-1.ll +++ b/llvm/test/CodeGen/X86/tlv-1.ll @@ -18,7 +18,7 @@ entry: ; rdar://10291355 define i32 @test() nounwind readonly ssp { entry: -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: movq _a@TLVP(%rip), ; CHECK: callq * ; CHECK: movl (%rax), [[REGISTER:%[a-z]+]] diff --git a/llvm/test/CodeGen/X86/trap.ll b/llvm/test/CodeGen/X86/trap.ll index 3f44be0b500..149c667c8cb 100644 --- a/llvm/test/CodeGen/X86/trap.ll +++ b/llvm/test/CodeGen/X86/trap.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s -; CHECK: test0: +; CHECK-LABEL: test0: ; CHECK: ud2 define i32 @test0() noreturn nounwind { entry: @@ -8,7 +8,7 @@ entry: unreachable } -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: int3 define i32 @test1() noreturn nounwind { entry: diff --git a/llvm/test/CodeGen/X86/trunc-to-bool.ll b/llvm/test/CodeGen/X86/trunc-to-bool.ll index 92b6859d1dc..3711cf1b21f 100644 --- a/llvm/test/CodeGen/X86/trunc-to-bool.ll +++ b/llvm/test/CodeGen/X86/trunc-to-bool.ll @@ -7,7 +7,7 @@ define zeroext i1 @test1(i32 %X) nounwind { %Y = trunc i32 %X to i1 ret i1 %Y } -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: andl $1, %eax define i1 @test2(i32 %val, i32 %mask) nounwind { @@ -21,7 +21,7 @@ ret_true: ret_false: ret i1 false } -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: btl %eax define i32 @test3(i8* %ptr) nounwind { @@ -33,7 +33,7 @@ cond_true: cond_false: ret i32 42 } -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: testb $1, (%eax) define i32 @test4(i8* %ptr) nounwind { @@ -44,7 +44,7 @@ cond_true: cond_false: ret i32 42 } -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: testb $1, 4(%esp) define i32 @test5(double %d) nounwind { @@ -55,5 +55,5 @@ cond_true: cond_false: ret i32 42 } -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: testb $1 diff --git a/llvm/test/CodeGen/X86/twoaddr-lea.ll b/llvm/test/CodeGen/X86/twoaddr-lea.ll index 9d58019b1a9..b5ca0275d8d 100644 --- a/llvm/test/CodeGen/X86/twoaddr-lea.ll +++ b/llvm/test/CodeGen/X86/twoaddr-lea.ll @@ -10,7 +10,7 @@ @G = external global i32 define i32 @test1(i32 %X) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: mov ; CHECK: leal 1(%rdi) %Z = add i32 %X, 1 @@ -23,7 +23,7 @@ define i32 @test1(i32 %X) nounwind { ; commutted (which would require inserting a copy). define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind { entry: -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: leal ; CHECK-NOT: leal ; CHECK-NOT: mov @@ -38,7 +38,7 @@ entry: ; rdar://9002648 define i64 @test3(i64 %x) nounwind readnone ssp { entry: -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: leaq (%rdi,%rdi), %rax ; CHECK-NOT: addq ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/X86/umul-with-overflow.ll b/llvm/test/CodeGen/X86/umul-with-overflow.ll index e5858de6ed7..52d1dc245ed 100644 --- a/llvm/test/CodeGen/X86/umul-with-overflow.ll +++ b/llvm/test/CodeGen/X86/umul-with-overflow.ll @@ -19,7 +19,7 @@ entry: %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2) %tmp2 = extractvalue { i32, i1 } %tmp1, 0 ret i32 %tmp2 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: addl ; CHECK-NEXT: addl ; CHECK-NEXT: ret @@ -31,7 +31,7 @@ entry: %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4) %tmp2 = extractvalue { i32, i1 } %tmp1, 0 ret i32 %tmp2 -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: addl ; CHECK: mull ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/X86/use-add-flags.ll b/llvm/test/CodeGen/X86/use-add-flags.ll index a0448ecee4f..fd57f5ca8d2 100644 --- a/llvm/test/CodeGen/X86/use-add-flags.ll +++ b/llvm/test/CodeGen/X86/use-add-flags.ll @@ -6,7 +6,7 @@ ; Use the flags on the add. -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: addl ; CHECK-NOT: test ; CHECK: cmovnsl @@ -25,7 +25,7 @@ declare void @foo(i32) ; Don't use the flags result of the and here, since the and has no ; other use. A simple test is better. -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: testb $16, {{%dil|%cl}} define void @test2(i32 %x) nounwind { @@ -41,7 +41,7 @@ false: ; Do use the flags result of the and here, since the and has another use. -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: andl $16, %e ; CHECK-NEXT: jne diff --git a/llvm/test/CodeGen/X86/v2f32.ll b/llvm/test/CodeGen/X86/v2f32.ll index ba548332916..f2bebf57d4d 100644 --- a/llvm/test/CodeGen/X86/v2f32.ll +++ b/llvm/test/CodeGen/X86/v2f32.ll @@ -10,20 +10,20 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind { store float %c, float* %P2 ret void -; X64: test1: +; X64-LABEL: test1: ; X64-NEXT: pshufd $1, %xmm0, %xmm1 ; X64-NEXT: addss %xmm0, %xmm1 ; X64-NEXT: movss %xmm1, (%rdi) ; X64-NEXT: ret -; W64: test1: +; W64-LABEL: test1: ; W64-NEXT: movdqa (%rcx), %xmm0 ; W64-NEXT: pshufd $1, %xmm0, %xmm1 ; W64-NEXT: addss %xmm0, %xmm1 ; W64-NEXT: movss %xmm1, (%rdx) ; W64-NEXT: ret -; X32: test1: +; X32-LABEL: test1: ; X32-NEXT: pshufd $1, %xmm0, %xmm1 ; X32-NEXT: addss %xmm0, %xmm1 ; X32-NEXT: movl 4(%esp), %eax @@ -36,16 +36,16 @@ define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounw %Z = fadd <2 x float> %Q, %R ret <2 x float> %Z -; X64: test2: +; X64-LABEL: test2: ; X64-NEXT: addps %xmm1, %xmm0 ; X64-NEXT: ret -; W64: test2: +; W64-LABEL: test2: ; W64-NEXT: movaps (%rcx), %xmm0 ; W64-NEXT: addps (%rdx), %xmm0 ; W64-NEXT: ret -; X32: test2: +; X32-LABEL: test2: ; X32: addps %xmm1, %xmm0 } @@ -54,16 +54,16 @@ define <2 x float> @test3(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B ret <2 x float> %C -; X64: test3: +; X64-LABEL: test3: ; X64-NEXT: addps %xmm0, %xmm0 ; X64-NEXT: ret -; W64: test3: +; W64-LABEL: test3: ; W64-NEXT: movaps (%rcx), %xmm0 ; W64-NEXT: addps %xmm0, %xmm0 ; W64-NEXT: ret -; X32: test3: +; X32-LABEL: test3: ; X32-NEXT: addps %xmm0, %xmm0 ; X32-NEXT: ret } @@ -71,16 +71,16 @@ define <2 x float> @test3(<4 x float> %A) nounwind { define <2 x float> @test4(<2 x float> %A) nounwind { %C = fadd <2 x float> %A, %A ret <2 x float> %C -; X64: test4: +; X64-LABEL: test4: ; X64-NEXT: addps %xmm0, %xmm0 ; X64-NEXT: ret -; W64: test4: +; W64-LABEL: test4: ; W64-NEXT: movaps (%rcx), %xmm0 ; W64-NEXT: addps %xmm0, %xmm0 ; W64-NEXT: ret -; X32: test4: +; X32-LABEL: test4: ; X32-NEXT: addps %xmm0, %xmm0 ; X32-NEXT: ret } @@ -95,18 +95,18 @@ BB: %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E -; X64: test5: +; X64-LABEL: test5: ; X64-NEXT: addps %xmm0, %xmm0 ; X64-NEXT: addps %xmm0, %xmm0 ; X64-NEXT: ret -; W64: test5: +; W64-LABEL: test5: ; W64-NEXT: movaps (%rcx), %xmm0 ; W64-NEXT: addps %xmm0, %xmm0 ; W64-NEXT: addps %xmm0, %xmm0 ; W64-NEXT: ret -; X32: test5: +; X32-LABEL: test5: ; X32-NEXT: addps %xmm0, %xmm0 ; X32-NEXT: addps %xmm0, %xmm0 ; X32-NEXT: ret diff --git a/llvm/test/CodeGen/X86/vec_compare-sse4.ll b/llvm/test/CodeGen/X86/vec_compare-sse4.ll index b4a4a4cfa7a..a08d9f5b11d 100644 --- a/llvm/test/CodeGen/X86/vec_compare-sse4.ll +++ b/llvm/test/CodeGen/X86/vec_compare-sse4.ll @@ -3,13 +3,13 @@ ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42 define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind { -; SSE42: test1: +; SSE42-LABEL: test1: ; SSE42: pcmpgtq ; SSE42: ret -; SSE41: test1: +; SSE41-LABEL: test1: ; SSE41-NOT: pcmpgtq ; SSE41: ret -; SSE2: test1: +; SSE2-LABEL: test1: ; SSE2-NOT: pcmpgtq ; SSE2: ret @@ -19,13 +19,13 @@ define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test2(<2 x i64> %A, <2 x i64> %B) nounwind { -; SSE42: test2: +; SSE42-LABEL: test2: ; SSE42: pcmpeqq ; SSE42: ret -; SSE41: test2: +; SSE41-LABEL: test2: ; SSE41: pcmpeqq ; SSE41: ret -; SSE2: test2: +; SSE2-LABEL: test2: ; SSE2-NOT: pcmpeqq ; SSE2: ret diff --git a/llvm/test/CodeGen/X86/vec_compare.ll b/llvm/test/CodeGen/X86/vec_compare.ll index fd5c234bb16..365fe92220b 100644 --- a/llvm/test/CodeGen/X86/vec_compare.ll +++ b/llvm/test/CodeGen/X86/vec_compare.ll @@ -2,7 +2,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: pcmpgtd ; CHECK: ret @@ -12,7 +12,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { } define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: pcmp ; CHECK: pcmp ; CHECK: pxor @@ -23,7 +23,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { } define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: pcmpgtd ; CHECK: movdqa ; CHECK: ret @@ -33,7 +33,7 @@ define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { } define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movdqa ; CHECK: pcmpgtd ; CHECK: ret @@ -43,7 +43,7 @@ define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { } define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: pcmpeqd ; CHECK: pshufd $-79 ; CHECK: pand @@ -54,7 +54,7 @@ define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: pcmpeqd ; CHECK: pshufd $-79 ; CHECK: pand @@ -72,7 +72,7 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 2147483648 ; CHECK-NEXT: .long 0 -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]] ; CHECK: pxor [[CONSTREG]] ; CHECK: pxor [[CONSTREG]] @@ -90,7 +90,7 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: pxor ; CHECK: pxor ; CHECK: pcmpgtd %xmm0 @@ -107,7 +107,7 @@ define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: pxor ; CHECK: pxor ; CHECK: pcmpgtd %xmm0 @@ -126,7 +126,7 @@ define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: pxor ; CHECK: pxor ; CHECK: pcmpgtd %xmm1 @@ -150,7 +150,7 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind { ; CHECK-NEXT: .long 2147483648 ; CHECK-NEXT: .long 2147483648 ; CHECK-NEXT: .long 2147483648 -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]] ; CHECK: pxor [[CONSTREG]] ; CHECK: pxor [[CONSTREG]] @@ -168,7 +168,7 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: pxor ; CHECK: pxor ; CHECK: pcmpgtd %xmm0 @@ -185,7 +185,7 @@ define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test13: +; CHECK-LABEL: test13: ; CHECK: pxor ; CHECK: pxor ; CHECK: pcmpgtd %xmm0 @@ -204,7 +204,7 @@ define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind { -; CHECK: test14: +; CHECK-LABEL: test14: ; CHECK: pxor ; CHECK: pxor ; CHECK: pcmpgtd %xmm1 diff --git a/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll b/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll index 59ceb2eb36d..56855d3c44e 100644 --- a/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll +++ b/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll @@ -77,4 +77,4 @@ entry: define <4 x i32> @sdiv_non_splat(<4 x i32> %x) { %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0> ret <4 x i32> %y -}
\ No newline at end of file +} diff --git a/llvm/test/CodeGen/X86/vec_splat-2.ll b/llvm/test/CodeGen/X86/vec_splat-2.ll index 5c668b7e5a5..9d82f97dca1 100644 --- a/llvm/test/CodeGen/X86/vec_splat-2.ll +++ b/llvm/test/CodeGen/X86/vec_splat-2.ll @@ -24,7 +24,7 @@ define void @test(<2 x i64>* %P, i8 %x) nounwind { store <2 x i64> %tmp73.upgrd.1, <2 x i64>* %P ret void -; CHECK: test: +; CHECK-LABEL: test: ; CHECK-NOT: pshufd ; CHECK: punpcklbw ; CHECK: punpcklbw diff --git a/llvm/test/CodeGen/X86/vec_splat.ll b/llvm/test/CodeGen/X86/vec_splat.ll index deedee80196..543c96ef3d4 100644 --- a/llvm/test/CodeGen/X86/vec_splat.ll +++ b/llvm/test/CodeGen/X86/vec_splat.ll @@ -11,10 +11,10 @@ define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind { store <4 x float> %tmp10, <4 x float>* %P ret void -; SSE2: test_v4sf: +; SSE2-LABEL: test_v4sf: ; SSE2: pshufd $0 -; SSE3: test_v4sf: +; SSE3-LABEL: test_v4sf: ; SSE3: pshufd $0 } @@ -26,9 +26,9 @@ define void @test_v2sd(<2 x double>* %P, <2 x double>* %Q, double %X) nounwind { store <2 x double> %tmp6, <2 x double>* %P ret void -; SSE2: test_v2sd: +; SSE2-LABEL: test_v2sd: ; SSE2: shufpd $0 -; SSE3: test_v2sd: +; SSE3-LABEL: test_v2sd: ; SSE3: movddup } diff --git a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll index c294df575a1..2eb911f1fc1 100644 --- a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll +++ b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll @@ -15,7 +15,7 @@ define i16 @test1(float %f) nounwind { %tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1] %tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1] ret i16 %tmp69 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: subss LCPI0_ ; CHECK: mulss LCPI0_ ; CHECK: minss LCPI0_ @@ -30,7 +30,7 @@ define i16 @test2(float %f) nounwind { %tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1] %tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1] ret i16 %tmp69 -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: addss LCPI1_ ; CHECK: mulss LCPI1_ ; CHECK: minss LCPI1_ @@ -55,7 +55,7 @@ define <4 x float> @test3(<4 x float> %A, float *%b, i32 %C) nounwind { %B = insertelement <4 x float> undef, float %a, i32 0 %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4) ret <4 x float> %X -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: roundss $4, (%eax), %xmm0 } @@ -65,7 +65,7 @@ define <4 x float> @test4(<4 x float> %A, float *%b, i32 %C) nounwind { %q = call <4 x float> @f() %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %q, <4 x float> %B, i32 4) ret <4 x float> %X -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movss (%eax), %xmm ; CHECK: call ; CHECK: roundss $4, %xmm{{.*}}, %xmm0 @@ -77,7 +77,7 @@ entry: %0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double 4.569870e+02, double 1.233210e+02>, i32 128) nounwind readnone ret <2 x double> %0 -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: mov ; CHECK: mov ; CHECK: cvtsi2sd diff --git a/llvm/test/CodeGen/X86/vec_uint_to_fp.ll b/llvm/test/CodeGen/X86/vec_uint_to_fp.ll index fe7fa2fe67d..ee20f1fcbd0 100644 --- a/llvm/test/CodeGen/X86/vec_uint_to_fp.ll +++ b/llvm/test/CodeGen/X86/vec_uint_to_fp.ll @@ -2,7 +2,7 @@ ; Test that we are not lowering uinttofp to scalars define <4 x float> @test1(<4 x i32> %A) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: cvtsd2ss ; CHECK: ret %C = uitofp <4 x i32> %A to <4 x float> diff --git a/llvm/test/CodeGen/X86/viabs.ll b/llvm/test/CodeGen/X86/viabs.ll index f748a14836c..0be00da83fd 100644 --- a/llvm/test/CodeGen/X86/viabs.ll +++ b/llvm/test/CodeGen/X86/viabs.ll @@ -3,18 +3,18 @@ ; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2 define <4 x i32> @test1(<4 x i32> %a) nounwind { -; SSE2: test1: +; SSE2-LABEL: test1: ; SSE2: movdqa ; SSE2: psrad $31 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test1: +; SSSE3-LABEL: test1: ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test1: +; AVX2-LABEL: test1: ; AVX2: vpabsd ; AVX2-NEXT: ret %tmp1neg = sub <4 x i32> zeroinitializer, %a @@ -24,18 +24,18 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind { } define <4 x i32> @test2(<4 x i32> %a) nounwind { -; SSE2: test2: +; SSE2-LABEL: test2: ; SSE2: movdqa ; SSE2: psrad $31 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test2: +; SSSE3-LABEL: test2: ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test2: +; AVX2-LABEL: test2: ; AVX2: vpabsd ; AVX2-NEXT: ret %tmp1neg = sub <4 x i32> zeroinitializer, %a @@ -45,18 +45,18 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind { } define <8 x i16> @test3(<8 x i16> %a) nounwind { -; SSE2: test3: +; SSE2-LABEL: test3: ; SSE2: movdqa ; SSE2: psraw $15 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test3: +; SSSE3-LABEL: test3: ; SSSE3: pabsw ; SSSE3-NEXT: ret -; AVX2: test3: +; AVX2-LABEL: test3: ; AVX2: vpabsw ; AVX2-NEXT: ret %tmp1neg = sub <8 x i16> zeroinitializer, %a @@ -66,18 +66,18 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind { } define <16 x i8> @test4(<16 x i8> %a) nounwind { -; SSE2: test4: +; SSE2-LABEL: test4: ; SSE2: pxor ; SSE2: pcmpgtb ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test4: +; SSSE3-LABEL: test4: ; SSSE3: pabsb ; SSSE3-NEXT: ret -; AVX2: test4: +; AVX2-LABEL: test4: ; AVX2: vpabsb ; AVX2-NEXT: ret %tmp1neg = sub <16 x i8> zeroinitializer, %a @@ -87,18 +87,18 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind { } define <4 x i32> @test5(<4 x i32> %a) nounwind { -; SSE2: test5: +; SSE2-LABEL: test5: ; SSE2: movdqa ; SSE2: psrad $31 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test5: +; SSSE3-LABEL: test5: ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test5: +; AVX2-LABEL: test5: ; AVX2: vpabsd ; AVX2-NEXT: ret %tmp1neg = sub <4 x i32> zeroinitializer, %a @@ -108,12 +108,12 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind { } define <8 x i32> @test6(<8 x i32> %a) nounwind { -; SSSE3: test6: +; SSSE3-LABEL: test6: ; SSSE3: pabsd ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test6: +; AVX2-LABEL: test6: ; AVX2: vpabsd {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <8 x i32> zeroinitializer, %a @@ -123,12 +123,12 @@ define <8 x i32> @test6(<8 x i32> %a) nounwind { } define <8 x i32> @test7(<8 x i32> %a) nounwind { -; SSSE3: test7: +; SSSE3-LABEL: test7: ; SSSE3: pabsd ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test7: +; AVX2-LABEL: test7: ; AVX2: vpabsd {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <8 x i32> zeroinitializer, %a @@ -138,12 +138,12 @@ define <8 x i32> @test7(<8 x i32> %a) nounwind { } define <16 x i16> @test8(<16 x i16> %a) nounwind { -; SSSE3: test8: +; SSSE3-LABEL: test8: ; SSSE3: pabsw ; SSSE3: pabsw ; SSSE3-NEXT: ret -; AVX2: test8: +; AVX2-LABEL: test8: ; AVX2: vpabsw {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <16 x i16> zeroinitializer, %a @@ -153,12 +153,12 @@ define <16 x i16> @test8(<16 x i16> %a) nounwind { } define <32 x i8> @test9(<32 x i8> %a) nounwind { -; SSSE3: test9: +; SSSE3-LABEL: test9: ; SSSE3: pabsb ; SSSE3: pabsb ; SSSE3-NEXT: ret -; AVX2: test9: +; AVX2-LABEL: test9: ; AVX2: vpabsb {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <32 x i8> zeroinitializer, %a @@ -168,12 +168,12 @@ define <32 x i8> @test9(<32 x i8> %a) nounwind { } define <8 x i32> @test10(<8 x i32> %a) nounwind { -; SSSE3: test10: +; SSSE3-LABEL: test10: ; SSSE3: pabsd ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test10: +; AVX2-LABEL: test10: ; AVX2: vpabsd {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <8 x i32> zeroinitializer, %a diff --git a/llvm/test/CodeGen/X86/vselect-minmax.ll b/llvm/test/CodeGen/X86/vselect-minmax.ll index cf654b6f205..25189f23e43 100644 --- a/llvm/test/CodeGen/X86/vselect-minmax.ll +++ b/llvm/test/CodeGen/X86/vselect-minmax.ll @@ -25,13 +25,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test1: +; SSE4-LABEL: test1: ; SSE4: pminsb -; AVX1: test1: +; AVX1-LABEL: test1: ; AVX1: vpminsb -; AVX2: test1: +; AVX2-LABEL: test1: ; AVX2: vpminsb } @@ -57,13 +57,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test2: +; SSE4-LABEL: test2: ; SSE4: pminsb -; AVX1: test2: +; AVX1-LABEL: test2: ; AVX1: vpminsb -; AVX2: test2: +; AVX2-LABEL: test2: ; AVX2: vpminsb } @@ -89,13 +89,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test3: +; SSE4-LABEL: test3: ; SSE4: pmaxsb -; AVX1: test3: +; AVX1-LABEL: test3: ; AVX1: vpmaxsb -; AVX2: test3: +; AVX2-LABEL: test3: ; AVX2: vpmaxsb } @@ -121,13 +121,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test4: +; SSE4-LABEL: test4: ; SSE4: pmaxsb -; AVX1: test4: +; AVX1-LABEL: test4: ; AVX1: vpmaxsb -; AVX2: test4: +; AVX2-LABEL: test4: ; AVX2: vpmaxsb } @@ -153,13 +153,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test5: +; SSE2-LABEL: test5: ; SSE2: pminub -; AVX1: test5: +; AVX1-LABEL: test5: ; AVX1: vpminub -; AVX2: test5: +; AVX2-LABEL: test5: ; AVX2: vpminub } @@ -185,13 +185,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test6: +; SSE2-LABEL: test6: ; SSE2: pminub -; AVX1: test6: +; AVX1-LABEL: test6: ; AVX1: vpminub -; AVX2: test6: +; AVX2-LABEL: test6: ; AVX2: vpminub } @@ -217,13 +217,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test7: +; SSE2-LABEL: test7: ; SSE2: pmaxub -; AVX1: test7: +; AVX1-LABEL: test7: ; AVX1: vpmaxub -; AVX2: test7: +; AVX2-LABEL: test7: ; AVX2: vpmaxub } @@ -249,13 +249,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test8: +; SSE2-LABEL: test8: ; SSE2: pmaxub -; AVX1: test8: +; AVX1-LABEL: test8: ; AVX1: vpmaxub -; AVX2: test8: +; AVX2-LABEL: test8: ; AVX2: vpmaxub } @@ -281,13 +281,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test9: +; SSE2-LABEL: test9: ; SSE2: pminsw -; AVX1: test9: +; AVX1-LABEL: test9: ; AVX1: vpminsw -; AVX2: test9: +; AVX2-LABEL: test9: ; AVX2: vpminsw } @@ -313,13 +313,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test10: +; SSE2-LABEL: test10: ; SSE2: pminsw -; AVX1: test10: +; AVX1-LABEL: test10: ; AVX1: vpminsw -; AVX2: test10: +; AVX2-LABEL: test10: ; AVX2: vpminsw } @@ -345,13 +345,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test11: +; SSE2-LABEL: test11: ; SSE2: pmaxsw -; AVX1: test11: +; AVX1-LABEL: test11: ; AVX1: vpmaxsw -; AVX2: test11: +; AVX2-LABEL: test11: ; AVX2: vpmaxsw } @@ -377,13 +377,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test12: +; SSE2-LABEL: test12: ; SSE2: pmaxsw -; AVX1: test12: +; AVX1-LABEL: test12: ; AVX1: vpmaxsw -; AVX2: test12: +; AVX2-LABEL: test12: ; AVX2: vpmaxsw } @@ -409,13 +409,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test13: +; SSE4-LABEL: test13: ; SSE4: pminuw -; AVX1: test13: +; AVX1-LABEL: test13: ; AVX1: vpminuw -; AVX2: test13: +; AVX2-LABEL: test13: ; AVX2: vpminuw } @@ -441,13 +441,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test14: +; SSE4-LABEL: test14: ; SSE4: pminuw -; AVX1: test14: +; AVX1-LABEL: test14: ; AVX1: vpminuw -; AVX2: test14: +; AVX2-LABEL: test14: ; AVX2: vpminuw } @@ -473,13 +473,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test15: +; SSE4-LABEL: test15: ; SSE4: pmaxuw -; AVX1: test15: +; AVX1-LABEL: test15: ; AVX1: vpmaxuw -; AVX2: test15: +; AVX2-LABEL: test15: ; AVX2: vpmaxuw } @@ -505,13 +505,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test16: +; SSE4-LABEL: test16: ; SSE4: pmaxuw -; AVX1: test16: +; AVX1-LABEL: test16: ; AVX1: vpmaxuw -; AVX2: test16: +; AVX2-LABEL: test16: ; AVX2: vpmaxuw } @@ -537,13 +537,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test17: +; SSE4-LABEL: test17: ; SSE4: pminsd -; AVX1: test17: +; AVX1-LABEL: test17: ; AVX1: vpminsd -; AVX2: test17: +; AVX2-LABEL: test17: ; AVX2: vpminsd } @@ -569,13 +569,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test18: +; SSE4-LABEL: test18: ; SSE4: pminsd -; AVX1: test18: +; AVX1-LABEL: test18: ; AVX1: vpminsd -; AVX2: test18: +; AVX2-LABEL: test18: ; AVX2: vpminsd } @@ -601,13 +601,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test19: +; SSE4-LABEL: test19: ; SSE4: pmaxsd -; AVX1: test19: +; AVX1-LABEL: test19: ; AVX1: vpmaxsd -; AVX2: test19: +; AVX2-LABEL: test19: ; AVX2: vpmaxsd } @@ -633,13 +633,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test20: +; SSE4-LABEL: test20: ; SSE4: pmaxsd -; AVX1: test20: +; AVX1-LABEL: test20: ; AVX1: vpmaxsd -; AVX2: test20: +; AVX2-LABEL: test20: ; AVX2: vpmaxsd } @@ -665,13 +665,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test21: +; SSE4-LABEL: test21: ; SSE4: pminud -; AVX1: test21: +; AVX1-LABEL: test21: ; AVX1: vpminud -; AVX2: test21: +; AVX2-LABEL: test21: ; AVX2: vpminud } @@ -697,13 +697,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test22: +; SSE4-LABEL: test22: ; SSE4: pminud -; AVX1: test22: +; AVX1-LABEL: test22: ; AVX1: vpminud -; AVX2: test22: +; AVX2-LABEL: test22: ; AVX2: vpminud } @@ -729,13 +729,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test23: +; SSE4-LABEL: test23: ; SSE4: pmaxud -; AVX1: test23: +; AVX1-LABEL: test23: ; AVX1: vpmaxud -; AVX2: test23: +; AVX2-LABEL: test23: ; AVX2: vpmaxud } @@ -761,13 +761,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test24: +; SSE4-LABEL: test24: ; SSE4: pmaxud -; AVX1: test24: +; AVX1-LABEL: test24: ; AVX1: vpmaxud -; AVX2: test24: +; AVX2-LABEL: test24: ; AVX2: vpmaxud } @@ -793,7 +793,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test25: +; AVX2-LABEL: test25: ; AVX2: vpminsb } @@ -819,7 +819,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test26: +; AVX2-LABEL: test26: ; AVX2: vpminsb } @@ -845,7 +845,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test27: +; AVX2-LABEL: test27: ; AVX2: vpmaxsb } @@ -871,7 +871,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test28: +; AVX2-LABEL: test28: ; AVX2: vpmaxsb } @@ -897,7 +897,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test29: +; AVX2-LABEL: test29: ; AVX2: vpminub } @@ -923,7 +923,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test30: +; AVX2-LABEL: test30: ; AVX2: vpminub } @@ -949,7 +949,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test31: +; AVX2-LABEL: test31: ; AVX2: vpmaxub } @@ -975,7 +975,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test32: +; AVX2-LABEL: test32: ; AVX2: vpmaxub } @@ -1001,7 +1001,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test33: +; AVX2-LABEL: test33: ; AVX2: vpminsw } @@ -1027,7 +1027,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test34: +; AVX2-LABEL: test34: ; AVX2: vpminsw } @@ -1053,7 +1053,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test35: +; AVX2-LABEL: test35: ; AVX2: vpmaxsw } @@ -1079,7 +1079,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test36: +; AVX2-LABEL: test36: ; AVX2: vpmaxsw } @@ -1105,7 +1105,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test37: +; AVX2-LABEL: test37: ; AVX2: vpminuw } @@ -1131,7 +1131,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test38: +; AVX2-LABEL: test38: ; AVX2: vpminuw } @@ -1157,7 +1157,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test39: +; AVX2-LABEL: test39: ; AVX2: vpmaxuw } @@ -1183,7 +1183,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test40: +; AVX2-LABEL: test40: ; AVX2: vpmaxuw } @@ -1209,7 +1209,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test41: +; AVX2-LABEL: test41: ; AVX2: vpminsd } @@ -1235,7 +1235,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test42: +; AVX2-LABEL: test42: ; AVX2: vpminsd } @@ -1261,7 +1261,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test43: +; AVX2-LABEL: test43: ; AVX2: vpmaxsd } @@ -1287,7 +1287,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test44: +; AVX2-LABEL: test44: ; AVX2: vpmaxsd } @@ -1313,7 +1313,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test45: +; AVX2-LABEL: test45: ; AVX2: vpminud } @@ -1339,7 +1339,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test46: +; AVX2-LABEL: test46: ; AVX2: vpminud } @@ -1365,7 +1365,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test47: +; AVX2-LABEL: test47: ; AVX2: vpmaxud } @@ -1391,7 +1391,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test48: +; AVX2-LABEL: test48: ; AVX2: vpmaxud } @@ -1417,13 +1417,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test49: +; SSE4-LABEL: test49: ; SSE4: pmaxsb -; AVX1: test49: +; AVX1-LABEL: test49: ; AVX1: vpmaxsb -; AVX2: test49: +; AVX2-LABEL: test49: ; AVX2: vpmaxsb } @@ -1449,13 +1449,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test50: +; SSE4-LABEL: test50: ; SSE4: pmaxsb -; AVX1: test50: +; AVX1-LABEL: test50: ; AVX1: vpmaxsb -; AVX2: test50: +; AVX2-LABEL: test50: ; AVX2: vpmaxsb } @@ -1481,13 +1481,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test51: +; SSE4-LABEL: test51: ; SSE4: pminsb -; AVX1: test51: +; AVX1-LABEL: test51: ; AVX1: vpminsb -; AVX2: test51: +; AVX2-LABEL: test51: ; AVX2: vpminsb } @@ -1513,13 +1513,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test52: +; SSE4-LABEL: test52: ; SSE4: pminsb -; AVX1: test52: +; AVX1-LABEL: test52: ; AVX1: vpminsb -; AVX2: test52: +; AVX2-LABEL: test52: ; AVX2: vpminsb } @@ -1545,13 +1545,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test53: +; SSE2-LABEL: test53: ; SSE2: pmaxub -; AVX1: test53: +; AVX1-LABEL: test53: ; AVX1: vpmaxub -; AVX2: test53: +; AVX2-LABEL: test53: ; AVX2: vpmaxub } @@ -1577,13 +1577,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test54: +; SSE2-LABEL: test54: ; SSE2: pmaxub -; AVX1: test54: +; AVX1-LABEL: test54: ; AVX1: vpmaxub -; AVX2: test54: +; AVX2-LABEL: test54: ; AVX2: vpmaxub } @@ -1609,13 +1609,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test55: +; SSE2-LABEL: test55: ; SSE2: pminub -; AVX1: test55: +; AVX1-LABEL: test55: ; AVX1: vpminub -; AVX2: test55: +; AVX2-LABEL: test55: ; AVX2: vpminub } @@ -1641,13 +1641,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test56: +; SSE2-LABEL: test56: ; SSE2: pminub -; AVX1: test56: +; AVX1-LABEL: test56: ; AVX1: vpminub -; AVX2: test56: +; AVX2-LABEL: test56: ; AVX2: vpminub } @@ -1673,13 +1673,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test57: +; SSE2-LABEL: test57: ; SSE2: pmaxsw -; AVX1: test57: +; AVX1-LABEL: test57: ; AVX1: vpmaxsw -; AVX2: test57: +; AVX2-LABEL: test57: ; AVX2: vpmaxsw } @@ -1705,13 +1705,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test58: +; SSE2-LABEL: test58: ; SSE2: pmaxsw -; AVX1: test58: +; AVX1-LABEL: test58: ; AVX1: vpmaxsw -; AVX2: test58: +; AVX2-LABEL: test58: ; AVX2: vpmaxsw } @@ -1737,13 +1737,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test59: +; SSE2-LABEL: test59: ; SSE2: pminsw -; AVX1: test59: +; AVX1-LABEL: test59: ; AVX1: vpminsw -; AVX2: test59: +; AVX2-LABEL: test59: ; AVX2: vpminsw } @@ -1769,13 +1769,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE2: test60: +; SSE2-LABEL: test60: ; SSE2: pminsw -; AVX1: test60: +; AVX1-LABEL: test60: ; AVX1: vpminsw -; AVX2: test60: +; AVX2-LABEL: test60: ; AVX2: vpminsw } @@ -1801,13 +1801,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test61: +; SSE4-LABEL: test61: ; SSE4: pmaxuw -; AVX1: test61: +; AVX1-LABEL: test61: ; AVX1: vpmaxuw -; AVX2: test61: +; AVX2-LABEL: test61: ; AVX2: vpmaxuw } @@ -1833,13 +1833,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test62: +; SSE4-LABEL: test62: ; SSE4: pmaxuw -; AVX1: test62: +; AVX1-LABEL: test62: ; AVX1: vpmaxuw -; AVX2: test62: +; AVX2-LABEL: test62: ; AVX2: vpmaxuw } @@ -1865,13 +1865,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test63: +; SSE4-LABEL: test63: ; SSE4: pminuw -; AVX1: test63: +; AVX1-LABEL: test63: ; AVX1: vpminuw -; AVX2: test63: +; AVX2-LABEL: test63: ; AVX2: vpminuw } @@ -1897,13 +1897,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test64: +; SSE4-LABEL: test64: ; SSE4: pminuw -; AVX1: test64: +; AVX1-LABEL: test64: ; AVX1: vpminuw -; AVX2: test64: +; AVX2-LABEL: test64: ; AVX2: vpminuw } @@ -1929,13 +1929,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test65: +; SSE4-LABEL: test65: ; SSE4: pmaxsd -; AVX1: test65: +; AVX1-LABEL: test65: ; AVX1: vpmaxsd -; AVX2: test65: +; AVX2-LABEL: test65: ; AVX2: vpmaxsd } @@ -1961,13 +1961,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test66: +; SSE4-LABEL: test66: ; SSE4: pmaxsd -; AVX1: test66: +; AVX1-LABEL: test66: ; AVX1: vpmaxsd -; AVX2: test66: +; AVX2-LABEL: test66: ; AVX2: vpmaxsd } @@ -1993,13 +1993,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test67: +; SSE4-LABEL: test67: ; SSE4: pminsd -; AVX1: test67: +; AVX1-LABEL: test67: ; AVX1: vpminsd -; AVX2: test67: +; AVX2-LABEL: test67: ; AVX2: vpminsd } @@ -2025,13 +2025,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test68: +; SSE4-LABEL: test68: ; SSE4: pminsd -; AVX1: test68: +; AVX1-LABEL: test68: ; AVX1: vpminsd -; AVX2: test68: +; AVX2-LABEL: test68: ; AVX2: vpminsd } @@ -2057,13 +2057,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test69: +; SSE4-LABEL: test69: ; SSE4: pmaxud -; AVX1: test69: +; AVX1-LABEL: test69: ; AVX1: vpmaxud -; AVX2: test69: +; AVX2-LABEL: test69: ; AVX2: vpmaxud } @@ -2089,13 +2089,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test70: +; SSE4-LABEL: test70: ; SSE4: pmaxud -; AVX1: test70: +; AVX1-LABEL: test70: ; AVX1: vpmaxud -; AVX2: test70: +; AVX2-LABEL: test70: ; AVX2: vpmaxud } @@ -2121,13 +2121,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test71: +; SSE4-LABEL: test71: ; SSE4: pminud -; AVX1: test71: +; AVX1-LABEL: test71: ; AVX1: vpminud -; AVX2: test71: +; AVX2-LABEL: test71: ; AVX2: vpminud } @@ -2153,13 +2153,13 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; SSE4: test72: +; SSE4-LABEL: test72: ; SSE4: pminud -; AVX1: test72: +; AVX1-LABEL: test72: ; AVX1: vpminud -; AVX2: test72: +; AVX2-LABEL: test72: ; AVX2: vpminud } @@ -2185,7 +2185,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test73: +; AVX2-LABEL: test73: ; AVX2: vpmaxsb } @@ -2211,7 +2211,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test74: +; AVX2-LABEL: test74: ; AVX2: vpmaxsb } @@ -2237,7 +2237,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test75: +; AVX2-LABEL: test75: ; AVX2: vpminsb } @@ -2263,7 +2263,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test76: +; AVX2-LABEL: test76: ; AVX2: vpminsb } @@ -2289,7 +2289,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test77: +; AVX2-LABEL: test77: ; AVX2: vpmaxub } @@ -2315,7 +2315,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test78: +; AVX2-LABEL: test78: ; AVX2: vpmaxub } @@ -2341,7 +2341,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test79: +; AVX2-LABEL: test79: ; AVX2: vpminub } @@ -2367,7 +2367,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test80: +; AVX2-LABEL: test80: ; AVX2: vpminub } @@ -2393,7 +2393,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test81: +; AVX2-LABEL: test81: ; AVX2: vpmaxsw } @@ -2419,7 +2419,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test82: +; AVX2-LABEL: test82: ; AVX2: vpmaxsw } @@ -2445,7 +2445,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test83: +; AVX2-LABEL: test83: ; AVX2: vpminsw } @@ -2471,7 +2471,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test84: +; AVX2-LABEL: test84: ; AVX2: vpminsw } @@ -2497,7 +2497,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test85: +; AVX2-LABEL: test85: ; AVX2: vpmaxuw } @@ -2523,7 +2523,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test86: +; AVX2-LABEL: test86: ; AVX2: vpmaxuw } @@ -2549,7 +2549,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test87: +; AVX2-LABEL: test87: ; AVX2: vpminuw } @@ -2575,7 +2575,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test88: +; AVX2-LABEL: test88: ; AVX2: vpminuw } @@ -2601,7 +2601,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test89: +; AVX2-LABEL: test89: ; AVX2: vpmaxsd } @@ -2627,7 +2627,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test90: +; AVX2-LABEL: test90: ; AVX2: vpmaxsd } @@ -2653,7 +2653,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test91: +; AVX2-LABEL: test91: ; AVX2: vpminsd } @@ -2679,7 +2679,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test92: +; AVX2-LABEL: test92: ; AVX2: vpminsd } @@ -2705,7 +2705,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test93: +; AVX2-LABEL: test93: ; AVX2: vpmaxud } @@ -2731,7 +2731,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test94: +; AVX2-LABEL: test94: ; AVX2: vpmaxud } @@ -2757,7 +2757,7 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test95: +; AVX2-LABEL: test95: ; AVX2: vpminud } @@ -2783,6 +2783,6 @@ vector.body: ; preds = %vector.body, %vecto for.end: ; preds = %vector.body ret void -; AVX2: test96: +; AVX2-LABEL: test96: ; AVX2: vpminud } diff --git a/llvm/test/CodeGen/X86/x86-64-and-mask.ll b/llvm/test/CodeGen/X86/x86-64-and-mask.ll index 8e8f6707226..1de406c2568 100644 --- a/llvm/test/CodeGen/X86/x86-64-and-mask.ll +++ b/llvm/test/CodeGen/X86/x86-64-and-mask.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin8" ; This should be a single mov, not a load of immediate + andq. -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: movl %edi, %eax define i64 @test(i64 %x) nounwind { diff --git a/llvm/test/CodeGen/X86/x86-64-psub.ll b/llvm/test/CodeGen/X86/x86-64-psub.ll index 7869a80b2a2..be09a4fcb82 100644 --- a/llvm/test/CodeGen/X86/x86-64-psub.ll +++ b/llvm/test/CodeGen/X86/x86-64-psub.ll @@ -26,7 +26,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubb: +; CHECK-LABEL: test_psubb: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] @@ -53,7 +53,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubw: +; CHECK-LABEL: test_psubw: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] @@ -81,7 +81,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubd: +; CHECK-LABEL: test_psubd: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] @@ -108,7 +108,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubsb: +; CHECK-LABEL: test_psubsb: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] @@ -135,7 +135,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubswv: +; CHECK-LABEL: test_psubswv: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] @@ -162,7 +162,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubusbv: +; CHECK-LABEL: test_psubusbv: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] @@ -189,7 +189,7 @@ entry: ret i64 %retval.0.extract.i15 } -; CHECK: test_psubuswv: +; CHECK-LABEL: test_psubuswv: ; CHECK: callq getFirstParam ; CHECK: callq getSecondParam ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]] diff --git a/llvm/test/CodeGen/X86/xor.ll b/llvm/test/CodeGen/X86/xor.ll index 574bb7817e4..b56ce0f52cc 100644 --- a/llvm/test/CodeGen/X86/xor.ll +++ b/llvm/test/CodeGen/X86/xor.ll @@ -7,7 +7,7 @@ define <4 x i32> @test1() nounwind { %tmp = xor <4 x i32> undef, undef ret <4 x i32> %tmp -; X32: test1: +; X32-LABEL: test1: ; X32: xorps %xmm0, %xmm0 ; X32: ret } @@ -16,7 +16,7 @@ define <4 x i32> @test1() nounwind { define i32 @test2() nounwind{ %tmp = xor i32 undef, undef ret i32 %tmp -; X32: test2: +; X32-LABEL: test2: ; X32: xorl %eax, %eax ; X32: ret } @@ -28,13 +28,13 @@ entry: %tmp4 = lshr i32 %tmp3, 1 ret i32 %tmp4 -; X64: test3: +; X64-LABEL: test3: ; X64: notl ; X64: andl ; X64: shrl ; X64: ret -; X32: test3: +; X32-LABEL: test3: ; X32: movl 8(%esp), %eax ; X32: notl %eax ; X32: andl 4(%esp), %eax @@ -57,10 +57,10 @@ bb: bb12: ret i32 %tmp3 -; X64: test4: +; X64-LABEL: test4: ; X64: notl [[REG:%[a-z]+]] ; X64: andl {{.*}}[[REG]] -; X32: test4: +; X32-LABEL: test4: ; X32: notl [[REG:%[a-z]+]] ; X32: andl {{.*}}[[REG]] } @@ -79,10 +79,10 @@ bb: br i1 %tmp10, label %bb12, label %bb bb12: ret i16 %tmp3 -; X64: test5: +; X64-LABEL: test5: ; X64: notl [[REG:%[a-z]+]] ; X64: andl {{.*}}[[REG]] -; X32: test5: +; X32-LABEL: test5: ; X32: notl [[REG:%[a-z]+]] ; X32: andl {{.*}}[[REG]] } @@ -101,10 +101,10 @@ bb: br i1 %tmp10, label %bb12, label %bb bb12: ret i8 %tmp3 -; X64: test6: +; X64-LABEL: test6: ; X64: notb [[REG:%[a-z]+]] ; X64: andb {{.*}}[[REG]] -; X32: test6: +; X32-LABEL: test6: ; X32: notb [[REG:%[a-z]+]] ; X32: andb {{.*}}[[REG]] } @@ -123,10 +123,10 @@ bb: br i1 %tmp10, label %bb12, label %bb bb12: ret i32 %tmp3 -; X64: test7: +; X64-LABEL: test7: ; X64: xorl $2147483646, [[REG:%[a-z]+]] ; X64: andl {{.*}}[[REG]] -; X32: test7: +; X32-LABEL: test7: ; X32: xorl $2147483646, [[REG:%[a-z]+]] ; X32: andl {{.*}}[[REG]] } @@ -137,9 +137,9 @@ entry: %t1 = sub i32 0, %a %t2 = add i32 %t1, -1 ret i32 %t2 -; X64: test8: +; X64-LABEL: test8: ; X64: notl {{%eax|%edi|%ecx}} -; X32: test8: +; X32-LABEL: test8: ; X32: notl %eax } @@ -147,10 +147,10 @@ define i32 @test9(i32 %a) nounwind { %1 = and i32 %a, 4096 %2 = xor i32 %1, 4096 ret i32 %2 -; X64: test9: +; X64-LABEL: test9: ; X64: notl [[REG:%[a-z]+]] ; X64: andl {{.*}}[[REG:%[a-z]+]] -; X32: test9: +; X32-LABEL: test9: ; X32: notl [[REG:%[a-z]+]] ; X32: andl {{.*}}[[REG:%[a-z]+]] } @@ -160,8 +160,8 @@ define <4 x i32> @test10(<4 x i32> %a) nounwind { %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096> %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096> ret <4 x i32> %2 -; X64: test10: +; X64-LABEL: test10: ; X64: andnps -; X32: test10: +; X32-LABEL: test10: ; X32: andnps } |
