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-rw-r--r--llvm/test/CodeGen/X86/vector-shuffle-v1.ll30
1 files changed, 7 insertions, 23 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
index 8104c07558a..d99d80e97b9 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=AVX512F
; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512bw -mattr=+avx512vl -mattr=+avx512dq| FileCheck %s --check-prefix=VL_BW_DQ
@@ -399,34 +400,17 @@ define i16 @shuf16i1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0(i16 %a) {
}
define i64 @shuf64i1_zero(i64 %a) {
-; AVX512F-LABEL: shuf64i1_zero:
-; AVX512F: # BB#0:
-; AVX512F-NEXT: pushq %rbp
-; AVX512F-NEXT: .Ltmp0:
-; AVX512F-NEXT: .cfi_def_cfa_offset 16
-; AVX512F-NEXT: .Ltmp1:
-; AVX512F-NEXT: .cfi_offset %rbp, -16
-; AVX512F-NEXT: movq %rsp, %rbp
-; AVX512F-NEXT: .Ltmp2:
-; AVX512F-NEXT: .cfi_def_cfa_register %rbp
-; AVX512F-NEXT: andq $-32, %rsp
-; AVX512F-NEXT: subq $32, %rsp
-; AVX512F-NEXT: movb $0, (%rsp)
-; AVX512F-NEXT: movl (%rsp), %ecx
-; AVX512F-NEXT: movq %rcx, %rax
-; AVX512F-NEXT: shlq $32, %rax
-; AVX512F-NEXT: orq %rcx, %rax
-; AVX512F-NEXT: movq %rbp, %rsp
-; AVX512F-NEXT: popq %rbp
-; AVX512F-NEXT: retq
-;
; VL_BW_DQ-LABEL: shuf64i1_zero:
; VL_BW_DQ: # BB#0:
-; VL_BW_DQ-NEXT: kxorq %k0, %k0, %k0
+; VL_BW_DQ-NEXT: kmovq %rdi, %k0
+; VL_BW_DQ-NEXT: vpmovm2b %k0, %zmm0
+; VL_BW_DQ-NEXT: vpbroadcastb %xmm0, %zmm0
+; VL_BW_DQ-NEXT: vpsllw $7, %zmm0, %zmm0
+; VL_BW_DQ-NEXT: vpmovb2m %zmm0, %k0
; VL_BW_DQ-NEXT: kmovq %k0, %rax
; VL_BW_DQ-NEXT: retq
%b = bitcast i64 %a to <64 x i1>
- %c = shufflevector < 64 x i1> zeroinitializer, <64 x i1> undef, <64 x i32> zeroinitializer
+ %c = shufflevector < 64 x i1> %b, <64 x i1> undef, <64 x i32> zeroinitializer
%d = bitcast <64 x i1> %c to i64
ret i64 %d
}
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