diff options
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-shift-shl-256.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 276 |
1 files changed, 138 insertions, 138 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-256.ll b/llvm/test/CodeGen/X86/vector-shift-shl-256.ll index a2cb3621d7b..712d9dbeef6 100644 --- a/llvm/test/CodeGen/X86/vector-shift-shl-256.ll +++ b/llvm/test/CodeGen/X86/vector-shift-shl-256.ll @@ -18,7 +18,7 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; AVX1-LABEL: var_shift_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpsllq %xmm2, %xmm3, %xmm4 @@ -33,12 +33,12 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: var_shift_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: var_shift_v4i64: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; XOPAVX1-NEXT: vpshlq %xmm2, %xmm3, %xmm2 @@ -47,22 +47,22 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_shift_v4i64: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: var_shift_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: var_shift_v4i64: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: var_shift_v4i64: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; X32-AVX1-NEXT: vpsllq %xmm2, %xmm3, %xmm4 @@ -77,7 +77,7 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: var_shift_v4i64: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <4 x i64> %a, %b @@ -86,7 +86,7 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; AVX1-LABEL: var_shift_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpslld $23, %xmm2, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216] @@ -102,12 +102,12 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: var_shift_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: var_shift_v8i32: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; XOPAVX1-NEXT: vpshld %xmm2, %xmm3, %xmm2 @@ -116,22 +116,22 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_shift_v8i32: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: var_shift_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: var_shift_v8i32: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: var_shift_v8i32: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; X32-AVX1-NEXT: vpslld $23, %xmm2, %xmm2 ; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216] @@ -147,7 +147,7 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: var_shift_v8i32: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <8 x i32> %a, %b @@ -156,7 +156,7 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX1-LABEL: var_shift_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm2, %xmm3 ; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2 @@ -191,7 +191,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: var_shift_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] @@ -205,7 +205,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: var_shift_v16i16: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; XOPAVX1-NEXT: vpshlw %xmm2, %xmm3, %xmm2 @@ -214,7 +214,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_shift_v16i16: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 ; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; XOPAVX2-NEXT: vpshlw %xmm2, %xmm3, %xmm2 @@ -223,7 +223,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; XOPAVX2-NEXT: retq ; ; AVX512DQ-LABEL: var_shift_v16i16: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512DQ-NEXT: vpsllvd %zmm1, %zmm0, %zmm0 @@ -231,7 +231,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: var_shift_v16i16: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 @@ -239,7 +239,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: var_shift_v16i16: -; AVX512DQVL: # BB#0: +; AVX512DQVL: # %bb.0: ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512DQVL-NEXT: vpsllvd %zmm1, %zmm0, %zmm0 @@ -247,12 +247,12 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX512DQVL-NEXT: retq ; ; AVX512BWVL-LABEL: var_shift_v16i16: -; AVX512BWVL: # BB#0: +; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vpsllvw %ymm1, %ymm0, %ymm0 ; AVX512BWVL-NEXT: retq ; ; X32-AVX1-LABEL: var_shift_v16i16: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; X32-AVX1-NEXT: vpsllw $12, %xmm2, %xmm3 ; X32-AVX1-NEXT: vpsllw $4, %xmm2, %xmm2 @@ -287,7 +287,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: var_shift_v16i16: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] @@ -305,7 +305,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX1-LABEL: var_shift_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vpsllw $4, %xmm2, %xmm3 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] @@ -336,7 +336,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: var_shift_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 ; AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 @@ -351,7 +351,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: var_shift_v32i8: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; XOPAVX1-NEXT: vpshlb %xmm2, %xmm3, %xmm2 @@ -360,7 +360,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_shift_v32i8: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 ; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; XOPAVX2-NEXT: vpshlb %xmm2, %xmm3, %xmm2 @@ -369,7 +369,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; XOPAVX2-NEXT: retq ; ; AVX512DQ-LABEL: var_shift_v32i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpsllw $5, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsllw $4, %ymm0, %ymm2 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 @@ -384,7 +384,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: var_shift_v32i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 @@ -392,7 +392,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: var_shift_v32i8: -; AVX512DQVL: # BB#0: +; AVX512DQVL: # %bb.0: ; AVX512DQVL-NEXT: vpsllw $5, %ymm1, %ymm1 ; AVX512DQVL-NEXT: vpsllw $4, %ymm0, %ymm2 ; AVX512DQVL-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 @@ -407,7 +407,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512DQVL-NEXT: retq ; ; AVX512BWVL-LABEL: var_shift_v32i8: -; AVX512BWVL: # BB#0: +; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero ; AVX512BWVL-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 @@ -415,7 +415,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512BWVL-NEXT: retq ; ; X32-AVX1-LABEL: var_shift_v32i8: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; X32-AVX1-NEXT: vpsllw $4, %xmm2, %xmm3 ; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] @@ -446,7 +446,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: var_shift_v32i8: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 ; X32-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 @@ -469,7 +469,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; AVX1-LABEL: splatvar_shift_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vpsllq %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 @@ -477,12 +477,12 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatvar_shift_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_shift_v4i64: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vpsllq %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 @@ -490,22 +490,22 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatvar_shift_v4i64: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatvar_shift_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatvar_shift_v4i64: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatvar_shift_v4i64: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; X32-AVX1-NEXT: vpsllq %xmm1, %xmm2, %xmm2 ; X32-AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 @@ -513,7 +513,7 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatvar_shift_v4i64: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer @@ -523,7 +523,7 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; AVX1-LABEL: splatvar_shift_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; AVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2 @@ -532,13 +532,13 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatvar_shift_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_shift_v8i32: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; XOPAVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2 @@ -547,25 +547,25 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatvar_shift_v8i32: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; XOPAVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatvar_shift_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; AVX512-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatvar_shift_v8i32: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; AVX512VL-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatvar_shift_v8i32: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; X32-AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; X32-AVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2 @@ -574,7 +574,7 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatvar_shift_v8i32: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; X32-AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl @@ -585,7 +585,7 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; AVX1-LABEL: splatvar_shift_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2 @@ -594,13 +594,13 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatvar_shift_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_shift_v16i16: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; XOPAVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2 @@ -609,25 +609,25 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatvar_shift_v16i16: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; XOPAVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatvar_shift_v16i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; AVX512-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatvar_shift_v16i16: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatvar_shift_v16i16: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; X32-AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; X32-AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2 @@ -636,7 +636,7 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatvar_shift_v16i16: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; X32-AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl @@ -647,7 +647,7 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX1-LABEL: splatvar_shift_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 @@ -676,7 +676,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatvar_shift_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastb %xmm1, %ymm1 ; AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 @@ -692,7 +692,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_shift_v32i8: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 @@ -702,7 +702,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatvar_shift_v32i8: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastb %xmm1, %ymm1 ; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 ; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm3 @@ -712,7 +712,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; XOPAVX2-NEXT: retq ; ; AVX512DQ-LABEL: splatvar_shift_v32i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpbroadcastb %xmm1, %ymm1 ; AVX512DQ-NEXT: vpsllw $4, %ymm0, %ymm2 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 @@ -728,7 +728,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: splatvar_shift_v32i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpbroadcastb %xmm1, %ymm1 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero @@ -737,7 +737,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: splatvar_shift_v32i8: -; AVX512DQVL: # BB#0: +; AVX512DQVL: # %bb.0: ; AVX512DQVL-NEXT: vpbroadcastb %xmm1, %ymm1 ; AVX512DQVL-NEXT: vpsllw $4, %ymm0, %ymm2 ; AVX512DQVL-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 @@ -753,7 +753,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512DQVL-NEXT: retq ; ; AVX512BWVL-LABEL: splatvar_shift_v32i8: -; AVX512BWVL: # BB#0: +; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vpbroadcastb %xmm1, %ymm1 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero @@ -762,7 +762,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; AVX512BWVL-NEXT: retq ; ; X32-AVX1-LABEL: splatvar_shift_v32i8: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; X32-AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 @@ -791,7 +791,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatvar_shift_v32i8: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpbroadcastb %xmm1, %ymm1 ; X32-AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 ; X32-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 @@ -816,7 +816,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind { ; AVX1-LABEL: constant_shift_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpsllq $62, %xmm1, %xmm2 ; AVX1-NEXT: vpsllq $31, %xmm1, %xmm1 @@ -828,12 +828,12 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: constant_shift_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: constant_shift_v4i64: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; XOPAVX1-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0 @@ -841,22 +841,22 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: constant_shift_v4i64: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: constant_shift_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: constant_shift_v4i64: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: constant_shift_v4i64: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,7,0,31,0,62,0] ; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 @@ -872,7 +872,7 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: constant_shift_v4i64: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllvq {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62> @@ -881,7 +881,7 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind { define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { ; AVX1-LABEL: constant_shift_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 @@ -889,12 +889,12 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: constant_shift_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: constant_shift_v8i32: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; XOPAVX1-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0 @@ -902,22 +902,22 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: constant_shift_v8i32: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: constant_shift_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: constant_shift_v8i32: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: constant_shift_v8i32: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm1 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X32-AVX1-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 @@ -925,7 +925,7 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: constant_shift_v8i32: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllvd {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> @@ -934,7 +934,7 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; AVX1-LABEL: constant_shift_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 @@ -942,12 +942,12 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: constant_shift_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: constant_shift_v16i16: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; XOPAVX1-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0 @@ -955,17 +955,17 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: constant_shift_v16i16: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512DQ-LABEL: constant_shift_v16i16: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: constant_shift_v16i16: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 @@ -973,17 +973,17 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: constant_shift_v16i16: -; AVX512DQVL: # BB#0: +; AVX512DQVL: # %bb.0: ; AVX512DQVL-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQVL-NEXT: retq ; ; AVX512BWVL-LABEL: constant_shift_v16i16: -; AVX512BWVL: # BB#0: +; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: retq ; ; X32-AVX1-LABEL: constant_shift_v16i16: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vpmullw {{\.LCPI.*}}, %xmm0, %xmm1 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X32-AVX1-NEXT: vpmullw {{\.LCPI.*}}, %xmm0, %xmm0 @@ -991,7 +991,7 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: constant_shift_v16i16: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpmullw {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> @@ -1000,7 +1000,7 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX1-LABEL: constant_shift_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] @@ -1027,7 +1027,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: constant_shift_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllw $4, %ymm0, %ymm1 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [8192,24640,41088,57536,49376,32928,16480,32,8192,24640,41088,57536,49376,32928,16480,32] @@ -1042,7 +1042,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: constant_shift_v32i8: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] ; XOPAVX1-NEXT: vpshlb %xmm2, %xmm1, %xmm1 @@ -1051,7 +1051,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: constant_shift_v32i8: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] ; XOPAVX2-NEXT: vpshlb %xmm2, %xmm1, %xmm1 @@ -1060,7 +1060,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; XOPAVX2-NEXT: retq ; ; AVX512DQ-LABEL: constant_shift_v32i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpsllw $4, %ymm0, %ymm1 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1 ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [8192,24640,41088,57536,49376,32928,16480,32,8192,24640,41088,57536,49376,32928,16480,32] @@ -1075,14 +1075,14 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: constant_shift_v32i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero ; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: constant_shift_v32i8: -; AVX512DQVL: # BB#0: +; AVX512DQVL: # %bb.0: ; AVX512DQVL-NEXT: vpsllw $4, %ymm0, %ymm1 ; AVX512DQVL-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1 ; AVX512DQVL-NEXT: vmovdqa {{.*#+}} ymm2 = [8192,24640,41088,57536,49376,32928,16480,32,8192,24640,41088,57536,49376,32928,16480,32] @@ -1097,14 +1097,14 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX512DQVL-NEXT: retq ; ; AVX512BWVL-LABEL: constant_shift_v32i8: -; AVX512BWVL: # BB#0: +; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0 ; AVX512BWVL-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BWVL-NEXT: retq ; ; X32-AVX1-LABEL: constant_shift_v32i8: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X32-AVX1-NEXT: vpsllw $4, %xmm1, %xmm2 ; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] @@ -1131,7 +1131,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: constant_shift_v32i8: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllw $4, %ymm0, %ymm1 ; X32-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm1, %ymm1 ; X32-AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [8192,24640,41088,57536,49376,32928,16480,32,8192,24640,41088,57536,49376,32928,16480,32] @@ -1154,7 +1154,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind { ; AVX1-LABEL: splatconstant_shift_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsllq $7, %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpsllq $7, %xmm0, %xmm0 @@ -1162,12 +1162,12 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatconstant_shift_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllq $7, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_shift_v4i64: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpsllq $7, %xmm0, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; XOPAVX1-NEXT: vpsllq $7, %xmm0, %xmm0 @@ -1175,22 +1175,22 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatconstant_shift_v4i64: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllq $7, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatconstant_shift_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllq $7, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_shift_v4i64: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllq $7, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatconstant_shift_v4i64: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vpsllq $7, %xmm0, %xmm1 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X32-AVX1-NEXT: vpsllq $7, %xmm0, %xmm0 @@ -1198,7 +1198,7 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatconstant_shift_v4i64: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllq $7, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7> @@ -1207,7 +1207,7 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind { define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind { ; AVX1-LABEL: splatconstant_shift_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpslld $5, %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpslld $5, %xmm0, %xmm0 @@ -1215,12 +1215,12 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatconstant_shift_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpslld $5, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_shift_v8i32: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpslld $5, %xmm0, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; XOPAVX1-NEXT: vpslld $5, %xmm0, %xmm0 @@ -1228,22 +1228,22 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatconstant_shift_v8i32: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpslld $5, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatconstant_shift_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpslld $5, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_shift_v8i32: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpslld $5, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatconstant_shift_v8i32: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vpslld $5, %xmm0, %xmm1 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X32-AVX1-NEXT: vpslld $5, %xmm0, %xmm0 @@ -1251,7 +1251,7 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatconstant_shift_v8i32: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpslld $5, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> @@ -1260,7 +1260,7 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind { define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind { ; AVX1-LABEL: splatconstant_shift_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsllw $3, %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpsllw $3, %xmm0, %xmm0 @@ -1268,12 +1268,12 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatconstant_shift_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_shift_v16i16: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpsllw $3, %xmm0, %xmm1 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; XOPAVX1-NEXT: vpsllw $3, %xmm0, %xmm0 @@ -1281,22 +1281,22 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatconstant_shift_v16i16: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatconstant_shift_v16i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllw $3, %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_shift_v16i16: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllw $3, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatconstant_shift_v16i16: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vpsllw $3, %xmm0, %xmm1 ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X32-AVX1-NEXT: vpsllw $3, %xmm0, %xmm0 @@ -1304,7 +1304,7 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatconstant_shift_v16i16: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> @@ -1313,7 +1313,7 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind { define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX1-LABEL: splatconstant_shift_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpsllw $3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248] @@ -1324,13 +1324,13 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: splatconstant_shift_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_shift_v32i8: -; XOPAVX1: # BB#0: +; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; XOPAVX1-NEXT: vpshlb %xmm2, %xmm1, %xmm1 @@ -1339,25 +1339,25 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind { ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: splatconstant_shift_v32i8: -; XOPAVX2: # BB#0: +; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; XOPAVX2-NEXT: retq ; ; AVX512-LABEL: splatconstant_shift_v32i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsllw $3, %ymm0, %ymm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_shift_v32i8: -; AVX512VL: # BB#0: +; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllw $3, %ymm0, %ymm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; X32-AVX1-LABEL: splatconstant_shift_v32i8: -; X32-AVX1: # BB#0: +; X32-AVX1: # %bb.0: ; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X32-AVX1-NEXT: vpsllw $3, %xmm1, %xmm1 ; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248] @@ -1368,7 +1368,7 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind { ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: splatconstant_shift_v32i8: -; X32-AVX2: # BB#0: +; X32-AVX2: # %bb.0: ; X32-AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX2-NEXT: retl |
