diff options
Diffstat (limited to 'llvm/test/CodeGen/X86/vec_minmax_uint.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_minmax_uint.ll | 416 |
1 files changed, 208 insertions, 208 deletions
diff --git a/llvm/test/CodeGen/X86/vec_minmax_uint.ll b/llvm/test/CodeGen/X86/vec_minmax_uint.ll index 9782384ebe1..cf764a2f346 100644 --- a/llvm/test/CodeGen/X86/vec_minmax_uint.ll +++ b/llvm/test/CodeGen/X86/vec_minmax_uint.ll @@ -13,7 +13,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-LABEL: max_gt_v2i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -32,7 +32,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_gt_v2i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm1, %xmm3 @@ -51,7 +51,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_gt_v2i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm2 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm1, %xmm3 @@ -63,7 +63,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_gt_v2i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 ; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 @@ -72,7 +72,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_gt_v2i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 @@ -81,7 +81,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_gt_v2i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 @@ -95,7 +95,7 @@ define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: max_gt_v4i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm3, %xmm5 ; SSE2-NEXT: pxor %xmm4, %xmm5 @@ -129,7 +129,7 @@ define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_gt_v4i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm8 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm3, %xmm5 @@ -163,7 +163,7 @@ define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_gt_v4i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm4 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm3, %xmm6 @@ -183,7 +183,7 @@ define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_gt_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 @@ -198,7 +198,7 @@ define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_gt_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastq {{.*}}(%rip), %ymm2 ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 @@ -207,7 +207,7 @@ define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_gt_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 @@ -220,7 +220,7 @@ define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-LABEL: max_gt_v4i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -232,17 +232,17 @@ define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_gt_v4i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxud %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_gt_v4i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxud %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: max_gt_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ugt <4 x i32> %a, %b @@ -252,7 +252,7 @@ define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) { define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-LABEL: max_gt_v8i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm3, %xmm6 ; SSE2-NEXT: pxor %xmm5, %xmm6 @@ -273,19 +273,19 @@ define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_gt_v8i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxud %xmm2, %xmm0 ; SSE41-NEXT: pmaxud %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_gt_v8i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxud %xmm2, %xmm0 ; SSE42-NEXT: pmaxud %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_gt_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpmaxud %xmm2, %xmm3, %xmm2 @@ -294,12 +294,12 @@ define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_gt_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_gt_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ugt <8 x i32> %a, %b @@ -309,7 +309,7 @@ define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) { define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-LABEL: max_gt_v8i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE2-NEXT: movdqa %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -321,17 +321,17 @@ define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_gt_v8i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxuw %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_gt_v8i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxuw %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: max_gt_v8i16: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ugt <8 x i16> %a, %b @@ -341,7 +341,7 @@ define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-LABEL: max_gt_v16i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE2-NEXT: movdqa %xmm3, %xmm6 ; SSE2-NEXT: pxor %xmm5, %xmm6 @@ -362,19 +362,19 @@ define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_gt_v16i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxuw %xmm2, %xmm0 ; SSE41-NEXT: pmaxuw %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_gt_v16i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxuw %xmm2, %xmm0 ; SSE42-NEXT: pmaxuw %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_gt_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpmaxuw %xmm2, %xmm3, %xmm2 @@ -383,12 +383,12 @@ define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_gt_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_gt_v16i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ugt <16 x i16> %a, %b @@ -398,12 +398,12 @@ define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) { define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) { ; SSE-LABEL: max_gt_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pmaxub %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v16i8: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ugt <16 x i8> %a, %b @@ -413,13 +413,13 @@ define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) { define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) { ; SSE-LABEL: max_gt_v32i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pmaxub %xmm2, %xmm0 ; SSE-NEXT: pmaxub %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: max_gt_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpmaxub %xmm2, %xmm3, %xmm2 @@ -428,12 +428,12 @@ define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_gt_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_gt_v32i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ugt <32 x i8> %a, %b @@ -447,7 +447,7 @@ define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) { define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-LABEL: max_ge_v2i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -469,7 +469,7 @@ define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_ge_v2i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm2, %xmm3 @@ -490,7 +490,7 @@ define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_ge_v2i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm2 ; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: pxor %xmm3, %xmm0 @@ -503,7 +503,7 @@ define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_ge_v2i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3 ; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm2 @@ -514,7 +514,7 @@ define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_ge_v2i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3 ; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 @@ -525,7 +525,7 @@ define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_ge_v2i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 @@ -539,7 +539,7 @@ define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: max_ge_v4i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: pxor %xmm7, %xmm4 @@ -579,7 +579,7 @@ define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_ge_v4i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm8 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm1, %xmm5 @@ -616,7 +616,7 @@ define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_ge_v4i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm4 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm1, %xmm6 @@ -639,7 +639,7 @@ define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_ge_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 @@ -657,7 +657,7 @@ define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_ge_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastq {{.*}}(%rip), %ymm2 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2 @@ -668,7 +668,7 @@ define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_ge_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 @@ -681,7 +681,7 @@ define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-LABEL: max_ge_v4i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm2 @@ -696,17 +696,17 @@ define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_ge_v4i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxud %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_ge_v4i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxud %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: max_ge_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp uge <4 x i32> %a, %b @@ -716,7 +716,7 @@ define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) { define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-LABEL: max_ge_v8i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: pxor %xmm6, %xmm4 @@ -742,19 +742,19 @@ define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_ge_v8i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxud %xmm2, %xmm0 ; SSE41-NEXT: pmaxud %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_ge_v8i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxud %xmm2, %xmm0 ; SSE42-NEXT: pmaxud %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_ge_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpmaxud %xmm2, %xmm3, %xmm2 @@ -763,12 +763,12 @@ define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_ge_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_ge_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp uge <8 x i32> %a, %b @@ -778,7 +778,7 @@ define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) { define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-LABEL: max_ge_v8i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: psubusw %xmm0, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm3 @@ -789,17 +789,17 @@ define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_ge_v8i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxuw %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_ge_v8i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxuw %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: max_ge_v8i16: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp uge <8 x i16> %a, %b @@ -809,7 +809,7 @@ define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-LABEL: max_ge_v16i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: psubusw %xmm1, %xmm4 ; SSE2-NEXT: pxor %xmm5, %xmm5 @@ -826,19 +826,19 @@ define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: max_ge_v16i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pmaxuw %xmm2, %xmm0 ; SSE41-NEXT: pmaxuw %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: max_ge_v16i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pmaxuw %xmm2, %xmm0 ; SSE42-NEXT: pmaxuw %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: max_ge_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpmaxuw %xmm2, %xmm3, %xmm2 @@ -847,12 +847,12 @@ define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_ge_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_ge_v16i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp uge <16 x i16> %a, %b @@ -862,12 +862,12 @@ define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) { define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) { ; SSE-LABEL: max_ge_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pmaxub %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v16i8: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp uge <16 x i8> %a, %b @@ -877,13 +877,13 @@ define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) { define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) { ; SSE-LABEL: max_ge_v32i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pmaxub %xmm2, %xmm0 ; SSE-NEXT: pmaxub %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: max_ge_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpmaxub %xmm2, %xmm3, %xmm2 @@ -892,12 +892,12 @@ define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: max_ge_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: max_ge_v32i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp uge <32 x i8> %a, %b @@ -911,7 +911,7 @@ define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) { define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-LABEL: min_lt_v2i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -930,7 +930,7 @@ define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_lt_v2i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm2, %xmm3 @@ -949,7 +949,7 @@ define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_lt_v2i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm2 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm2, %xmm3 @@ -961,7 +961,7 @@ define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_lt_v2i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3 ; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm2 @@ -970,7 +970,7 @@ define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_lt_v2i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3 ; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 @@ -979,7 +979,7 @@ define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_lt_v2i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 @@ -993,7 +993,7 @@ define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: min_lt_v4i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: pxor %xmm4, %xmm5 @@ -1027,7 +1027,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_lt_v4i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm8 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm1, %xmm5 @@ -1061,7 +1061,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_lt_v4i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm4 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm1, %xmm6 @@ -1081,7 +1081,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_lt_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 @@ -1096,7 +1096,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_lt_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastq {{.*}}(%rip), %ymm2 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2 @@ -1105,7 +1105,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_lt_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 @@ -1118,7 +1118,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-LABEL: min_lt_v4i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -1130,17 +1130,17 @@ define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_lt_v4i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminud %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_lt_v4i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminud %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: min_lt_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ult <4 x i32> %a, %b @@ -1150,7 +1150,7 @@ define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) { define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-LABEL: min_lt_v8i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: pxor %xmm4, %xmm5 @@ -1170,19 +1170,19 @@ define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_lt_v8i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminud %xmm2, %xmm0 ; SSE41-NEXT: pminud %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_lt_v8i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminud %xmm2, %xmm0 ; SSE42-NEXT: pminud %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_lt_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpminud %xmm2, %xmm3, %xmm2 @@ -1191,12 +1191,12 @@ define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_lt_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_lt_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ult <8 x i32> %a, %b @@ -1206,7 +1206,7 @@ define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) { define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-LABEL: min_lt_v8i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -1218,17 +1218,17 @@ define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_lt_v8i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminuw %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_lt_v8i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminuw %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: min_lt_v8i16: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ult <8 x i16> %a, %b @@ -1238,7 +1238,7 @@ define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-LABEL: min_lt_v16i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: pxor %xmm4, %xmm5 @@ -1258,19 +1258,19 @@ define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_lt_v16i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminuw %xmm2, %xmm0 ; SSE41-NEXT: pminuw %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_lt_v16i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminuw %xmm2, %xmm0 ; SSE42-NEXT: pminuw %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_lt_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpminuw %xmm2, %xmm3, %xmm2 @@ -1279,12 +1279,12 @@ define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_lt_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_lt_v16i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ult <16 x i16> %a, %b @@ -1294,12 +1294,12 @@ define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) { define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) { ; SSE-LABEL: min_lt_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pminub %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v16i8: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ult <16 x i8> %a, %b @@ -1309,13 +1309,13 @@ define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) { define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) { ; SSE-LABEL: min_lt_v32i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pminub %xmm2, %xmm0 ; SSE-NEXT: pminub %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: min_lt_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpminub %xmm2, %xmm3, %xmm2 @@ -1324,12 +1324,12 @@ define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_lt_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_lt_v32i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ult <32 x i8> %a, %b @@ -1343,7 +1343,7 @@ define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) { define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-LABEL: min_le_v2i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3 @@ -1365,7 +1365,7 @@ define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_le_v2i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm1, %xmm3 @@ -1386,7 +1386,7 @@ define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_le_v2i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm2 ; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm1, %xmm0 @@ -1400,7 +1400,7 @@ define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_le_v2i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 ; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 @@ -1411,7 +1411,7 @@ define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_le_v2i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 @@ -1422,7 +1422,7 @@ define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_le_v2i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 @@ -1436,7 +1436,7 @@ define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: min_le_v4i64: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: pxor %xmm7, %xmm4 @@ -1476,7 +1476,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_le_v4i64: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: movdqa %xmm0, %xmm8 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] ; SSE41-NEXT: movdqa %xmm3, %xmm5 @@ -1513,7 +1513,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_le_v4i64: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: movdqa %xmm0, %xmm4 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm3, %xmm6 @@ -1536,7 +1536,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_le_v4i64: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 @@ -1554,7 +1554,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_le_v4i64: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastq {{.*}}(%rip), %ymm2 ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 @@ -1565,7 +1565,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_le_v4i64: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 @@ -1578,7 +1578,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-LABEL: min_le_v4i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm2 @@ -1593,17 +1593,17 @@ define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_le_v4i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminud %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_le_v4i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminud %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: min_le_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ule <4 x i32> %a, %b @@ -1613,7 +1613,7 @@ define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) { define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-LABEL: min_le_v8i32: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: pxor %xmm6, %xmm4 @@ -1639,19 +1639,19 @@ define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_le_v8i32: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminud %xmm2, %xmm0 ; SSE41-NEXT: pminud %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_le_v8i32: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminud %xmm2, %xmm0 ; SSE42-NEXT: pminud %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_le_v8i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpminud %xmm2, %xmm3, %xmm2 @@ -1660,12 +1660,12 @@ define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_le_v8i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_le_v8i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ule <8 x i32> %a, %b @@ -1675,7 +1675,7 @@ define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) { define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-LABEL: min_le_v8i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: psubusw %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm3 @@ -1686,17 +1686,17 @@ define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_le_v8i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminuw %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_le_v8i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminuw %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: min_le_v8i16: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ule <8 x i16> %a, %b @@ -1706,7 +1706,7 @@ define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-LABEL: min_le_v16i16: -; SSE2: # BB#0: +; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: psubusw %xmm3, %xmm4 ; SSE2-NEXT: pxor %xmm6, %xmm6 @@ -1725,19 +1725,19 @@ define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-NEXT: retq ; ; SSE41-LABEL: min_le_v16i16: -; SSE41: # BB#0: +; SSE41: # %bb.0: ; SSE41-NEXT: pminuw %xmm2, %xmm0 ; SSE41-NEXT: pminuw %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; SSE42-LABEL: min_le_v16i16: -; SSE42: # BB#0: +; SSE42: # %bb.0: ; SSE42-NEXT: pminuw %xmm2, %xmm0 ; SSE42-NEXT: pminuw %xmm3, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: min_le_v16i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpminuw %xmm2, %xmm3, %xmm2 @@ -1746,12 +1746,12 @@ define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_le_v16i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_le_v16i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ule <16 x i16> %a, %b @@ -1761,12 +1761,12 @@ define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) { define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) { ; SSE-LABEL: min_le_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pminub %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v16i8: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = icmp ule <16 x i8> %a, %b @@ -1776,13 +1776,13 @@ define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) { define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) { ; SSE-LABEL: min_le_v32i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pminub %xmm2, %xmm0 ; SSE-NEXT: pminub %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: min_le_v32i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpminub %xmm2, %xmm3, %xmm2 @@ -1791,12 +1791,12 @@ define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: min_le_v32i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: min_le_v32i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %1 = icmp ule <32 x i8> %a, %b @@ -1810,12 +1810,12 @@ define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) { define <2 x i64> @max_gt_v2i64c() { ; SSE-LABEL: max_gt_v2i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v2i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7] ; AVX-NEXT: retq %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 @@ -1827,13 +1827,13 @@ define <2 x i64> @max_gt_v2i64c() { define <4 x i64> @max_gt_v4i64c() { ; SSE-LABEL: max_gt_v4i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v4i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7] ; AVX-NEXT: retq %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 @@ -1845,12 +1845,12 @@ define <4 x i64> @max_gt_v4i64c() { define <4 x i32> @max_gt_v4i32c() { ; SSE-LABEL: max_gt_v4i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v4i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] ; AVX-NEXT: retq %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 @@ -1862,13 +1862,13 @@ define <4 x i32> @max_gt_v4i32c() { define <8 x i32> @max_gt_v8i32c() { ; SSE-LABEL: max_gt_v8i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v8i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7] ; AVX-NEXT: retq %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 @@ -1880,12 +1880,12 @@ define <8 x i32> @max_gt_v8i32c() { define <8 x i16> @max_gt_v8i16c() { ; SSE-LABEL: max_gt_v8i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v8i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] ; AVX-NEXT: retq %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 @@ -1897,13 +1897,13 @@ define <8 x i16> @max_gt_v8i16c() { define <16 x i16> @max_gt_v16i16c() { ; SSE-LABEL: max_gt_v16i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8] ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v16i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8] ; AVX-NEXT: retq %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 @@ -1915,12 +1915,12 @@ define <16 x i16> @max_gt_v16i16c() { define <16 x i8> @max_gt_v16i8c() { ; SSE-LABEL: max_gt_v16i8c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] ; SSE-NEXT: retq ; ; AVX-LABEL: max_gt_v16i8c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] ; AVX-NEXT: retq %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 @@ -1932,12 +1932,12 @@ define <16 x i8> @max_gt_v16i8c() { define <2 x i64> @max_ge_v2i64c() { ; SSE-LABEL: max_ge_v2i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v2i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7] ; AVX-NEXT: retq %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 @@ -1949,13 +1949,13 @@ define <2 x i64> @max_ge_v2i64c() { define <4 x i64> @max_ge_v4i64c() { ; SSE-LABEL: max_ge_v4i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v4i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7] ; AVX-NEXT: retq %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 @@ -1967,12 +1967,12 @@ define <4 x i64> @max_ge_v4i64c() { define <4 x i32> @max_ge_v4i32c() { ; SSE-LABEL: max_ge_v4i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v4i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] ; AVX-NEXT: retq %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 @@ -1984,13 +1984,13 @@ define <4 x i32> @max_ge_v4i32c() { define <8 x i32> @max_ge_v8i32c() { ; SSE-LABEL: max_ge_v8i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v8i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7] ; AVX-NEXT: retq %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 @@ -2002,12 +2002,12 @@ define <8 x i32> @max_ge_v8i32c() { define <8 x i16> @max_ge_v8i16c() { ; SSE-LABEL: max_ge_v8i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v8i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] ; AVX-NEXT: retq %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 @@ -2019,13 +2019,13 @@ define <8 x i16> @max_ge_v8i16c() { define <16 x i16> @max_ge_v16i16c() { ; SSE-LABEL: max_ge_v16i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8] ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v16i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8] ; AVX-NEXT: retq %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 @@ -2037,12 +2037,12 @@ define <16 x i16> @max_ge_v16i16c() { define <16 x i8> @max_ge_v16i8c() { ; SSE-LABEL: max_ge_v16i8c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] ; SSE-NEXT: retq ; ; AVX-LABEL: max_ge_v16i8c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] ; AVX-NEXT: retq %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 @@ -2054,12 +2054,12 @@ define <16 x i8> @max_ge_v16i8c() { define <2 x i64> @min_lt_v2i64c() { ; SSE-LABEL: min_lt_v2i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v2i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1] ; AVX-NEXT: retq %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 @@ -2071,13 +2071,13 @@ define <2 x i64> @min_lt_v2i64c() { define <4 x i64> @min_lt_v4i64c() { ; SSE-LABEL: min_lt_v4i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v4i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1] ; AVX-NEXT: retq %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 @@ -2089,12 +2089,12 @@ define <4 x i64> @min_lt_v4i64c() { define <4 x i32> @min_lt_v4i32c() { ; SSE-LABEL: min_lt_v4i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v4i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] ; AVX-NEXT: retq %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 @@ -2106,13 +2106,13 @@ define <4 x i32> @min_lt_v4i32c() { define <8 x i32> @min_lt_v8i32c() { ; SSE-LABEL: min_lt_v8i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v8i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1] ; AVX-NEXT: retq %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 @@ -2124,12 +2124,12 @@ define <8 x i32> @min_lt_v8i32c() { define <8 x i16> @min_lt_v8i16c() { ; SSE-LABEL: min_lt_v8i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v8i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1] ; AVX-NEXT: retq %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 @@ -2141,13 +2141,13 @@ define <8 x i16> @min_lt_v8i16c() { define <16 x i16> @min_lt_v16i16c() { ; SSE-LABEL: min_lt_v16i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v16i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0] ; AVX-NEXT: retq %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 @@ -2159,12 +2159,12 @@ define <16 x i16> @min_lt_v16i16c() { define <16 x i8> @min_lt_v16i8c() { ; SSE-LABEL: min_lt_v16i8c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] ; SSE-NEXT: retq ; ; AVX-LABEL: min_lt_v16i8c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] ; AVX-NEXT: retq %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 @@ -2176,12 +2176,12 @@ define <16 x i8> @min_lt_v16i8c() { define <2 x i64> @min_le_v2i64c() { ; SSE-LABEL: min_le_v2i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v2i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1] ; AVX-NEXT: retq %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 @@ -2193,13 +2193,13 @@ define <2 x i64> @min_le_v2i64c() { define <4 x i64> @min_le_v4i64c() { ; SSE-LABEL: min_le_v4i64c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v4i64c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1] ; AVX-NEXT: retq %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 @@ -2211,12 +2211,12 @@ define <4 x i64> @min_le_v4i64c() { define <4 x i32> @min_le_v4i32c() { ; SSE-LABEL: min_le_v4i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v4i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] ; AVX-NEXT: retq %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 @@ -2228,13 +2228,13 @@ define <4 x i32> @min_le_v4i32c() { define <8 x i32> @min_le_v8i32c() { ; SSE-LABEL: min_le_v8i32c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v8i32c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1] ; AVX-NEXT: retq %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 @@ -2246,12 +2246,12 @@ define <8 x i32> @min_le_v8i32c() { define <8 x i16> @min_le_v8i16c() { ; SSE-LABEL: min_le_v8i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v8i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1] ; AVX-NEXT: retq %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 @@ -2263,13 +2263,13 @@ define <8 x i16> @min_le_v8i16c() { define <16 x i16> @min_le_v16i16c() { ; SSE-LABEL: min_le_v16i16c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v16i16c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0] ; AVX-NEXT: retq %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 @@ -2281,12 +2281,12 @@ define <16 x i16> @min_le_v16i16c() { define <16 x i8> @min_le_v16i8c() { ; SSE-LABEL: min_le_v16i8c: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] ; SSE-NEXT: retq ; ; AVX-LABEL: min_le_v16i8c: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] ; AVX-NEXT: retq %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 |
