summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/vec_cast3.ll
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/X86/vec_cast3.ll')
-rw-r--r--llvm/test/CodeGen/X86/vec_cast3.ll87
1 files changed, 87 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vec_cast3.ll b/llvm/test/CodeGen/X86/vec_cast3.ll
index 82b8c00c0a2..4148f7eb0f4 100644
--- a/llvm/test/CodeGen/X86/vec_cast3.ll
+++ b/llvm/test/CodeGen/X86/vec_cast3.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE
define <2 x float> @cvt_v2i8_v2f32(<2 x i8> %src) {
; CHECK-LABEL: cvt_v2i8_v2f32:
@@ -7,6 +8,12 @@ define <2 x float> @cvt_v2i8_v2f32(<2 x i8> %src) {
; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2i8_v2f32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = sitofp <2 x i8> %src to <2 x float>
ret <2 x float> %res
}
@@ -17,6 +24,12 @@ define <2 x float> @cvt_v2i16_v2f32(<2 x i16> %src) {
; CHECK-NEXT: vpmovsxwd %xmm0, %xmm0
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2i16_v2f32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vpmovsxwd %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = sitofp <2 x i16> %src to <2 x float>
ret <2 x float> %res
}
@@ -26,6 +39,11 @@ define <2 x float> @cvt_v2i32_v2f32(<2 x i32> %src) {
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2i32_v2f32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = sitofp <2 x i32> %src to <2 x float>
ret <2 x float> %res
}
@@ -36,6 +54,12 @@ define <2 x float> @cvt_v2u8_v2f32(<2 x i8> %src) {
; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2u8_v2f32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = uitofp <2 x i8> %src to <2 x float>
ret <2 x float> %res
}
@@ -46,6 +70,12 @@ define <2 x float> @cvt_v2u16_v2f32(<2 x i16> %src) {
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2u16_v2f32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = uitofp <2 x i16> %src to <2 x float>
ret <2 x float> %res
}
@@ -59,6 +89,15 @@ define <2 x float> @cvt_v2u32_v2f32(<2 x i32> %src) {
; CHECK-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2u32_v2f32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; CHECK-WIDE-NEXT: vmovdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
+; CHECK-WIDE-NEXT: vpor %xmm1, %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vsubpd %xmm1, %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vcvtpd2ps %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = uitofp <2 x i32> %src to <2 x float>
ret <2 x float> %res
}
@@ -69,6 +108,12 @@ define <2 x i8> @cvt_v2f32_v2i8(<2 x float> %src) {
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2f32_v2i8:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
+; CHECK-WIDE-NEXT: retl
%res = fptosi <2 x float> %src to <2 x i8>
ret <2 x i8> %res
}
@@ -79,6 +124,12 @@ define <2 x i16> @cvt_v2f32_v2i16(<2 x float> %src) {
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2f32_v2i16:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
+; CHECK-WIDE-NEXT: retl
%res = fptosi <2 x float> %src to <2 x i16>
ret <2 x i16> %res
}
@@ -88,6 +139,11 @@ define <2 x i32> @cvt_v2f32_v2i32(<2 x float> %src) {
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2f32_v2i32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = fptosi <2 x float> %src to <2 x i32>
ret <2 x i32> %res
}
@@ -98,6 +154,12 @@ define <2 x i8> @cvt_v2f32_v2u8(<2 x float> %src) {
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2f32_v2u8:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
+; CHECK-WIDE-NEXT: retl
%res = fptoui <2 x float> %src to <2 x i8>
ret <2 x i8> %res
}
@@ -108,6 +170,12 @@ define <2 x i16> @cvt_v2f32_v2u16(<2 x float> %src) {
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2f32_v2u16:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
+; CHECK-WIDE-NEXT: retl
%res = fptoui <2 x float> %src to <2 x i16>
ret <2 x i16> %res
}
@@ -123,6 +191,17 @@ define <2 x i32> @cvt_v2f32_v2u32(<2 x float> %src) {
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: cvt_v2f32_v2u32:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vmovaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; CHECK-WIDE-NEXT: vcmpltps %xmm1, %xmm0, %xmm2
+; CHECK-WIDE-NEXT: vsubps %xmm1, %xmm0, %xmm1
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm1, %xmm1
+; CHECK-WIDE-NEXT: vxorps LCPI11_1, %xmm1, %xmm1
+; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
+; CHECK-WIDE-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; CHECK-WIDE-NEXT: retl
%res = fptoui <2 x float> %src to <2 x i32>
ret <2 x i32> %res
}
@@ -135,6 +214,14 @@ define <32 x i8> @PR40146(<4 x i64> %x) {
; CHECK-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT: retl
+;
+; CHECK-WIDE-LABEL: PR40146:
+; CHECK-WIDE: ## %bb.0:
+; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; CHECK-WIDE-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-WIDE-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; CHECK-WIDE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-WIDE-NEXT: retl
%perm = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
%t1 = bitcast <4 x i64> %perm to <32 x i8>
%t2 = shufflevector <32 x i8> %t1, <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 32, i32 1, i32 32, i32 2, i32 32, i32 3, i32 32, i32 4, i32 32, i32 5, i32 32, i32 6, i32 32, i32 7, i32 32, i32 16, i32 48, i32 17, i32 48, i32 18, i32 48, i32 19, i32 48, i32 20, i32 48, i32 21, i32 48, i32 22, i32 48, i32 23, i32 48>
OpenPOWER on IntegriCloud