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-rw-r--r--llvm/test/CodeGen/X86/tbm-schedule.ll130
1 files changed, 65 insertions, 65 deletions
diff --git a/llvm/test/CodeGen/X86/tbm-schedule.ll b/llvm/test/CodeGen/X86/tbm-schedule.ll
index 5c73c4b49dc..b8f9bb08f3e 100644
--- a/llvm/test/CodeGen/X86/tbm-schedule.ll
+++ b/llvm/test/CodeGen/X86/tbm-schedule.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+tbm | FileCheck %s --check-prefix=GENERIC
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+tbm | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=bdver2 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=bdver3 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER3
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=bdver4 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER4
@@ -16,12 +16,12 @@ define i32 @test_x86_tbm_bextri_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_bextri_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
-; BDVER2-NEXT: # sched: [2:1.00]
; BDVER2-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
-; BDVER2-NEXT: # sched: [7:1.00]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: # sched: [6:0.50]
+; BDVER2-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
+; BDVER2-NEXT: # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_bextri_u32:
; BDVER3: # %bb.0:
@@ -57,12 +57,12 @@ define i64 @test_x86_tbm_bextri_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_bextri_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
-; BDVER2-NEXT: # sched: [2:1.00]
; BDVER2-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
-; BDVER2-NEXT: # sched: [7:1.00]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: # sched: [6:0.50]
+; BDVER2-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
+; BDVER2-NEXT: # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_bextri_u64:
; BDVER3: # %bb.0:
@@ -96,10 +96,10 @@ define i32 @test_x86_tbm_blcfill_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcfill_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcfilll %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blcfilll (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcfilll %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcfill_u32:
; BDVER3: # %bb.0:
@@ -133,10 +133,10 @@ define i64 @test_x86_tbm_blcfill_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcfill_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcfillq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blcfillq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcfillq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcfill_u64:
; BDVER3: # %bb.0:
@@ -170,10 +170,10 @@ define i32 @test_x86_tbm_blci_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blci_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcil %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blcil (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcil %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blci_u32:
; BDVER3: # %bb.0:
@@ -209,10 +209,10 @@ define i64 @test_x86_tbm_blci_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blci_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blciq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blciq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blciq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blci_u64:
; BDVER3: # %bb.0:
@@ -248,10 +248,10 @@ define i32 @test_x86_tbm_blcic_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcic_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcicl %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blcicl (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcicl %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcic_u32:
; BDVER3: # %bb.0:
@@ -287,10 +287,10 @@ define i64 @test_x86_tbm_blcic_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcic_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcicq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blcicq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcicq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcic_u64:
; BDVER3: # %bb.0:
@@ -326,10 +326,10 @@ define i32 @test_x86_tbm_blcmsk_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcmsk_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcmskl %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blcmskl (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcmskl %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcmsk_u32:
; BDVER3: # %bb.0:
@@ -363,10 +363,10 @@ define i64 @test_x86_tbm_blcmsk_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcmsk_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcmskq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blcmskq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcmskq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcmsk_u64:
; BDVER3: # %bb.0:
@@ -400,10 +400,10 @@ define i32 @test_x86_tbm_blcs_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcs_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcsl %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blcsl (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcsl %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcs_u32:
; BDVER3: # %bb.0:
@@ -437,10 +437,10 @@ define i64 @test_x86_tbm_blcs_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blcs_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blcsq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blcsq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blcsq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blcs_u64:
; BDVER3: # %bb.0:
@@ -474,10 +474,10 @@ define i32 @test_x86_tbm_blsfill_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blsfill_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blsfilll %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blsfilll (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blsfilll %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blsfill_u32:
; BDVER3: # %bb.0:
@@ -511,10 +511,10 @@ define i64 @test_x86_tbm_blsfill_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blsfill_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blsfillq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blsfillq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blsfillq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blsfill_u64:
; BDVER3: # %bb.0:
@@ -548,10 +548,10 @@ define i32 @test_x86_tbm_blsic_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blsic_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blsicl %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: blsicl (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blsicl %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blsic_u32:
; BDVER3: # %bb.0:
@@ -587,10 +587,10 @@ define i64 @test_x86_tbm_blsic_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_blsic_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: blsicq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: blsicq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: blsicq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_blsic_u64:
; BDVER3: # %bb.0:
@@ -626,10 +626,10 @@ define i32 @test_x86_tbm_t1mskc_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_t1mskc_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: t1mskcl %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: t1mskcl (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: t1mskcl %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_t1mskc_u32:
; BDVER3: # %bb.0:
@@ -665,10 +665,10 @@ define i64 @test_x86_tbm_t1mskc_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_t1mskc_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: t1mskcq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: t1mskcq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: t1mskcq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_t1mskc_u64:
; BDVER3: # %bb.0:
@@ -704,10 +704,10 @@ define i32 @test_x86_tbm_tzmsk_u32(i32 %a0, i32* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_tzmsk_u32:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: tzmskl %edi, %ecx # sched: [1:0.33]
; BDVER2-NEXT: tzmskl (%rsi), %eax # sched: [6:0.50]
-; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: tzmskl %edi, %ecx # sched: [2:0.50]
+; BDVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_tzmsk_u32:
; BDVER3: # %bb.0:
@@ -743,10 +743,10 @@ define i64 @test_x86_tbm_tzmsk_u64(i64 %a0, i64* nocapture %p1) nounwind {
;
; BDVER2-LABEL: test_x86_tbm_tzmsk_u64:
; BDVER2: # %bb.0:
-; BDVER2-NEXT: tzmskq %rdi, %rcx # sched: [1:0.33]
; BDVER2-NEXT: tzmskq (%rsi), %rax # sched: [6:0.50]
-; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.33]
-; BDVER2-NEXT: retq # sched: [1:1.00]
+; BDVER2-NEXT: tzmskq %rdi, %rcx # sched: [2:0.50]
+; BDVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
+; BDVER2-NEXT: retq # sched: [5:1.00]
;
; BDVER3-LABEL: test_x86_tbm_tzmsk_u64:
; BDVER3: # %bb.0:
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