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-rw-r--r--llvm/test/CodeGen/X86/signbit-shift.ll25
1 files changed, 25 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/signbit-shift.ll b/llvm/test/CodeGen/X86/signbit-shift.ll
index b22c1a34a3d..510bfe515ac 100644
--- a/llvm/test/CodeGen/X86/signbit-shift.ll
+++ b/llvm/test/CodeGen/X86/signbit-shift.ll
@@ -228,3 +228,28 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
ret <4 x i32> %r
}
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shrl $31, %edi
+; CHECK-NEXT: xorl $43, %edi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
+ %sh = lshr i32 %x, 31
+ %r = sub i32 43, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42]
+; CHECK-NEXT: psubd %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ ret <4 x i32> %r
+}
+
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