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-rw-r--r--llvm/test/CodeGen/X86/min-legal-vector-width.ll129
1 files changed, 0 insertions, 129 deletions
diff --git a/llvm/test/CodeGen/X86/min-legal-vector-width.ll b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
index 49dae99268d..8bfd448f201 100644
--- a/llvm/test/CodeGen/X86/min-legal-vector-width.ll
+++ b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
@@ -1116,132 +1116,3 @@ define void @trunc_packus_v16i32_v16i8_store(<16 x i32>* %p, <16 x i8>* %q) "min
store <16 x i8> %f, <16 x i8>* %q
ret void
}
-
-define <32 x i8> @trunc_packus_v32i32_v32i8(<32 x i32>* %p) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_packus_v32i32_v32i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: vpmaxsd 96(%rdi), %ymm0, %ymm1
-; CHECK-NEXT: vpmovusdb %ymm1, %xmm1
-; CHECK-NEXT: vpmaxsd 64(%rdi), %ymm0, %ymm2
-; CHECK-NEXT: vpmovusdb %ymm2, %xmm2
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; CHECK-NEXT: vpmaxsd 32(%rdi), %ymm0, %ymm2
-; CHECK-NEXT: vpmovusdb %ymm2, %xmm2
-; CHECK-NEXT: vpmaxsd (%rdi), %ymm0, %ymm0
-; CHECK-NEXT: vpmovusdb %ymm0, %xmm0
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
- %a = load <32 x i32>, <32 x i32>* %p
- %b = icmp slt <32 x i32> %a, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
- %c = select <32 x i1> %b, <32 x i32> %a, <32 x i32> <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
- %d = icmp sgt <32 x i32> %c, zeroinitializer
- %e = select <32 x i1> %d, <32 x i32> %c, <32 x i32> zeroinitializer
- %f = trunc <32 x i32> %e to <32 x i8>
- ret <32 x i8> %f
-}
-
-define <8 x i8> @trunc_packus_v8i64_v8i8(<8 x i64> %a0) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_packus_v8i64_v8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; CHECK-NEXT: vpmaxsq %ymm2, %ymm1, %ymm1
-; CHECK-NEXT: vpmovusqb %ymm1, %xmm1
-; CHECK-NEXT: vpmaxsq %ymm2, %ymm0, %ymm0
-; CHECK-NEXT: vpmovusqb %ymm0, %xmm0
-; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %1 = icmp slt <8 x i64> %a0, <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %2 = select <8 x i1> %1, <8 x i64> %a0, <8 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %3 = icmp sgt <8 x i64> %2, zeroinitializer
- %4 = select <8 x i1> %3, <8 x i64> %2, <8 x i64> zeroinitializer
- %5 = trunc <8 x i64> %4 to <8 x i8>
- ret <8 x i8> %5
-}
-
-define void @trunc_packus_v8i64_v8i8_store(<8 x i64> %a0, <8 x i8> *%p1) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_packus_v8i64_v8i8_store:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; CHECK-NEXT: vpmaxsq %ymm2, %ymm1, %ymm1
-; CHECK-NEXT: vpmovusqb %ymm1, %xmm1
-; CHECK-NEXT: vpmaxsq %ymm2, %ymm0, %ymm0
-; CHECK-NEXT: vpmovusqb %ymm0, %xmm0
-; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: vmovq %xmm0, (%rdi)
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %1 = icmp slt <8 x i64> %a0, <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %2 = select <8 x i1> %1, <8 x i64> %a0, <8 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %3 = icmp sgt <8 x i64> %2, zeroinitializer
- %4 = select <8 x i1> %3, <8 x i64> %2, <8 x i64> zeroinitializer
- %5 = trunc <8 x i64> %4 to <8 x i8>
- store <8 x i8> %5, <8 x i8> *%p1
- ret void
-}
-
-define <8 x i8> @trunc_ssat_v8i64_v8i8(<8 x i64> %a0) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_ssat_v8i64_v8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpmovsqb %ymm1, %xmm1
-; CHECK-NEXT: vpmovsqb %ymm0, %xmm0
-; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %1 = icmp slt <8 x i64> %a0, <i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127>
- %2 = select <8 x i1> %1, <8 x i64> %a0, <8 x i64> <i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127>
- %3 = icmp sgt <8 x i64> %2, <i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128>
- %4 = select <8 x i1> %3, <8 x i64> %2, <8 x i64> <i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128>
- %5 = trunc <8 x i64> %4 to <8 x i8>
- ret <8 x i8> %5
-}
-
-define void @trunc_ssat_v8i64_v8i8_store(<8 x i64> %a0, <8 x i8> *%p1) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_ssat_v8i64_v8i8_store:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpmovsqb %ymm1, %xmm1
-; CHECK-NEXT: vpmovsqb %ymm0, %xmm0
-; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: vmovq %xmm0, (%rdi)
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %1 = icmp slt <8 x i64> %a0, <i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127>
- %2 = select <8 x i1> %1, <8 x i64> %a0, <8 x i64> <i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127>
- %3 = icmp sgt <8 x i64> %2, <i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128>
- %4 = select <8 x i1> %3, <8 x i64> %2, <8 x i64> <i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128>
- %5 = trunc <8 x i64> %4 to <8 x i8>
- store <8 x i8> %5, <8 x i8> *%p1
- ret void
-}
-
-define <8 x i8> @trunc_usat_v8i64_v8i8(<8 x i64> %a0) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_usat_v8i64_v8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpmovusqb %ymm1, %xmm1
-; CHECK-NEXT: vpmovusqb %ymm0, %xmm0
-; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %1 = icmp ult <8 x i64> %a0, <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %2 = select <8 x i1> %1, <8 x i64> %a0, <8 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %3 = trunc <8 x i64> %2 to <8 x i8>
- ret <8 x i8> %3
-}
-
-define void @trunc_usat_v8i64_v8i8_store(<8 x i64> %a0, <8 x i8> *%p1) "min-legal-vector-width"="256" {
-; CHECK-LABEL: trunc_usat_v8i64_v8i8_store:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpmovusqb %ymm1, %xmm1
-; CHECK-NEXT: vpmovusqb %ymm0, %xmm0
-; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: vmovq %xmm0, (%rdi)
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %1 = icmp ult <8 x i64> %a0, <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %2 = select <8 x i1> %1, <8 x i64> %a0, <8 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
- %3 = trunc <8 x i64> %2 to <8 x i8>
- store <8 x i8> %3, <8 x i8> *%p1
- ret void
-}
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