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Diffstat (limited to 'llvm/test/CodeGen/X86/combine-sra.ll')
-rw-r--r--llvm/test/CodeGen/X86/combine-sra.ll56
1 files changed, 28 insertions, 28 deletions
diff --git a/llvm/test/CodeGen/X86/combine-sra.ll b/llvm/test/CodeGen/X86/combine-sra.ll
index fb16faa30a9..436f48e14b0 100644
--- a/llvm/test/CodeGen/X86/combine-sra.ll
+++ b/llvm/test/CodeGen/X86/combine-sra.ll
@@ -5,12 +5,12 @@
; fold (sra 0, x) -> 0
define <4 x i32> @combine_vec_ashr_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_zero:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_zero:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <4 x i32> zeroinitializer, %x
@@ -20,12 +20,12 @@ define <4 x i32> @combine_vec_ashr_zero(<4 x i32> %x) {
; fold (sra -1, x) -> -1
define <4 x i32> @combine_vec_ashr_allones(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_allones:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_allones:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
@@ -35,11 +35,11 @@ define <4 x i32> @combine_vec_ashr_allones(<4 x i32> %x) {
; fold (sra x, c >= size(x)) -> undef
define <4 x i32> @combine_vec_ashr_outofrange0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_outofrange0:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_outofrange0:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
ret <4 x i32> %1
@@ -47,11 +47,11 @@ define <4 x i32> @combine_vec_ashr_outofrange0(<4 x i32> %x) {
define <4 x i32> @combine_vec_ashr_outofrange1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_outofrange1:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_outofrange1:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
ret <4 x i32> %1
@@ -60,11 +60,11 @@ define <4 x i32> @combine_vec_ashr_outofrange1(<4 x i32> %x) {
; fold (sra x, 0) -> x
define <4 x i32> @combine_vec_ashr_by_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_by_zero:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_by_zero:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, zeroinitializer
ret <4 x i32> %1
@@ -73,12 +73,12 @@ define <4 x i32> @combine_vec_ashr_by_zero(<4 x i32> %x) {
; fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
define <4 x i32> @combine_vec_ashr_ashr0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_ashr0:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: psrad $6, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_ashr0:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpsrad $6, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
@@ -88,7 +88,7 @@ define <4 x i32> @combine_vec_ashr_ashr0(<4 x i32> %x) {
define <4 x i32> @combine_vec_ashr_ashr1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_ashr1:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrad $10, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
@@ -102,7 +102,7 @@ define <4 x i32> @combine_vec_ashr_ashr1(<4 x i32> %x) {
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_ashr1:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
@@ -112,12 +112,12 @@ define <4 x i32> @combine_vec_ashr_ashr1(<4 x i32> %x) {
define <4 x i32> @combine_vec_ashr_ashr2(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_ashr2:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: psrad $31, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_ashr2:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 17, i32 18, i32 19, i32 20>
@@ -127,7 +127,7 @@ define <4 x i32> @combine_vec_ashr_ashr2(<4 x i32> %x) {
define <4 x i32> @combine_vec_ashr_ashr3(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_ashr3:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrad $27, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
@@ -146,7 +146,7 @@ define <4 x i32> @combine_vec_ashr_ashr3(<4 x i32> %x) {
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_ashr3:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
@@ -158,7 +158,7 @@ define <4 x i32> @combine_vec_ashr_ashr3(<4 x i32> %x) {
; fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
define <4 x i32> @combine_vec_ashr_trunc_and(<4 x i32> %x, <4 x i64> %y) {
; SSE-LABEL: combine_vec_ashr_trunc_and:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: movaps %xmm1, %xmm2
@@ -181,7 +181,7 @@ define <4 x i32> @combine_vec_ashr_trunc_and(<4 x i32> %x, <4 x i64> %y) {
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_trunc_and:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
; AVX-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
@@ -198,7 +198,7 @@ define <4 x i32> @combine_vec_ashr_trunc_and(<4 x i32> %x, <4 x i64> %y) {
; if c1 is equal to the number of bits the trunc removes
define <4 x i32> @combine_vec_ashr_trunc_lshr(<4 x i64> %x) {
; SSE-LABEL: combine_vec_ashr_trunc_lshr:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: psrlq $32, %xmm1
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
@@ -214,7 +214,7 @@ define <4 x i32> @combine_vec_ashr_trunc_lshr(<4 x i64> %x) {
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_trunc_lshr:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpsrlq $32, %ymm0, %ymm0
; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
@@ -231,7 +231,7 @@ define <4 x i32> @combine_vec_ashr_trunc_lshr(<4 x i64> %x) {
; if c1 is equal to the number of bits the trunc removes
define <4 x i32> @combine_vec_ashr_trunc_ashr(<4 x i64> %x) {
; SSE-LABEL: combine_vec_ashr_trunc_ashr:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE-NEXT: psrad $31, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
@@ -248,7 +248,7 @@ define <4 x i32> @combine_vec_ashr_trunc_ashr(<4 x i64> %x) {
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_trunc_ashr:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,3,2,3,5,7,6,7]
; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
@@ -263,7 +263,7 @@ define <4 x i32> @combine_vec_ashr_trunc_ashr(<4 x i64> %x) {
; If the sign bit is known to be zero, switch this to a SRL.
define <4 x i32> @combine_vec_ashr_positive(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_ashr_positive:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
@@ -285,7 +285,7 @@ define <4 x i32> @combine_vec_ashr_positive(<4 x i32> %x, <4 x i32> %y) {
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_positive:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
@@ -296,12 +296,12 @@ define <4 x i32> @combine_vec_ashr_positive(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @combine_vec_ashr_positive_splat(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_ashr_positive_splat:
-; SSE: # BB#0:
+; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_positive_splat:
-; AVX: # BB#0:
+; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = and <4 x i32> %x, <i32 1023, i32 1023, i32 1023, i32 1023>
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