diff options
Diffstat (limited to 'llvm/test/CodeGen/X86/codegen-prepare-extload.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/codegen-prepare-extload.ll | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll index 9b27c33a80f..6619ebec2f8 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll +++ b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll @@ -12,13 +12,13 @@ ; CHECK: movsbl ({{%rdi|%rcx}}), %eax ; ; OPTALL-LABEL: @foo -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 ; OPTALL: store i32 [[ZEXT]], i32* %q ; OPTALL: ret define void @foo(i8* %p, i32* %q) { entry: - %t = load i8* %p + %t = load i8, i8* %p %a = icmp slt i8 %t, 20 br i1 %a, label %true, label %false true: @@ -32,7 +32,7 @@ false: ; Check that we manage to form a zextload is an operation with only one ; argument to explicitly extend is in the the way. ; OPTALL-LABEL: @promoteOneArg -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2 ; Make sure the operation is not promoted when the promotion pass is disabled. @@ -42,7 +42,7 @@ false: ; OPTALL: ret define void @promoteOneArg(i8* %p, i32* %q) { entry: - %t = load i8* %p + %t = load i8, i8* %p %add = add nuw i8 %t, 2 %a = icmp slt i8 %t, 20 br i1 %a, label %true, label %false @@ -58,7 +58,7 @@ false: ; argument to explicitly extend is in the the way. ; Version with sext. ; OPTALL-LABEL: @promoteOneArgSExt -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2 @@ -67,7 +67,7 @@ false: ; OPTALL: ret define void @promoteOneArgSExt(i8* %p, i32* %q) { entry: - %t = load i8* %p + %t = load i8, i8* %p %add = add nsw i8 %t, 2 %a = icmp slt i8 %t, 20 br i1 %a, label %true, label %false @@ -90,7 +90,7 @@ false: ; transformation, the regular heuristic does not apply the optimization. ; ; OPTALL-LABEL: @promoteTwoArgZext -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32 @@ -106,7 +106,7 @@ false: ; OPTALL: ret define void @promoteTwoArgZext(i8* %p, i32* %q, i8 %b) { entry: - %t = load i8* %p + %t = load i8, i8* %p %add = add nuw i8 %t, %b %a = icmp slt i8 %t, 20 br i1 %a, label %true, label %false @@ -122,7 +122,7 @@ false: ; arguments to explicitly extend is in the the way. ; Version with sext. ; OPTALL-LABEL: @promoteTwoArgSExt -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; ; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32 ; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32 @@ -137,7 +137,7 @@ false: ; OPTALL: ret define void @promoteTwoArgSExt(i8* %p, i32* %q, i8 %b) { entry: - %t = load i8* %p + %t = load i8, i8* %p %add = add nsw i8 %t, %b %a = icmp slt i8 %t, 20 br i1 %a, label %true, label %false @@ -152,7 +152,7 @@ false: ; Check that we do not a zextload if we need to introduce more than ; one additional extension. ; OPTALL-LABEL: @promoteThreeArgZext -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32 @@ -172,7 +172,7 @@ false: ; OPTALL: ret define void @promoteThreeArgZext(i8* %p, i32* %q, i8 %b, i8 %c) { entry: - %t = load i8* %p + %t = load i8, i8* %p %tmp = add nuw i8 %t, %b %add = add nuw i8 %tmp, %c %a = icmp slt i8 %t, 20 @@ -188,7 +188,7 @@ false: ; Check that we manage to form a zextload after promoting and merging ; two extensions. ; OPTALL-LABEL: @promoteMergeExtArgZExt -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32 @@ -206,7 +206,7 @@ false: ; OPTALL: ret define void @promoteMergeExtArgZExt(i8* %p, i32* %q, i16 %b) { entry: - %t = load i8* %p + %t = load i8, i8* %p %ext = zext i8 %t to i16 %add = add nuw i16 %ext, %b %a = icmp slt i8 %t, 20 @@ -223,7 +223,7 @@ false: ; two extensions. ; Version with sext. ; OPTALL-LABEL: @promoteMergeExtArgSExt -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p ; ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32 @@ -240,7 +240,7 @@ false: ; OPTALL: ret define void @promoteMergeExtArgSExt(i8* %p, i32* %q, i16 %b) { entry: - %t = load i8* %p + %t = load i8, i8* %p %ext = zext i8 %t to i16 %add = add nsw i16 %ext, %b %a = icmp slt i8 %t, 20 @@ -284,11 +284,11 @@ false: ; 3 identical zext of %ld. The extensions will be CSE'ed by SDag. ; ; OPTALL-LABEL: @severalPromotions -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %addr1 +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %addr1 ; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 ; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 ; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 -; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32* %addr2 +; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, i32* %addr2 ; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_1]] ; We do not combine this one: see 2.b. @@ -308,9 +308,9 @@ false: ; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]]) ; OPTALL: ret define void @severalPromotions(i8* %addr1, i32* %addr2, i8 %a, i32 %b) { - %ld = load i8* %addr1 + %ld = load i8, i8* %addr1 %zextld = zext i8 %ld to i32 - %ld2 = load i32* %addr2 + %ld2 = load i32, i32* %addr2 %add = add nsw i32 %ld2, %zextld %sextadd = sext i32 %add to i64 %zexta = zext i8 %a to i32 @@ -345,7 +345,7 @@ entry: ; to an instruction. ; This used to cause a crash. ; OPTALL-LABEL: @promotionOfArgEndsUpInValue -; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16* %addr +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, i16* %addr ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32]* @c, i64 0, i64 1), i32* @a) to i32) @@ -356,7 +356,7 @@ entry: ; OPTALL-NEXT: ret i32 [[RES]] define i32 @promotionOfArgEndsUpInValue(i16* %addr) { entry: - %val = load i16* %addr + %val = load i16, i16* %addr %add = add nuw nsw i16 %val, zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32]* @c, i64 0, i64 1), i32* @a) to i16) %conv3 = sext i16 %add to i32 ret i32 %conv3 |
