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Diffstat (limited to 'llvm/test/CodeGen/X86/build-vector-128.ll')
-rw-r--r--llvm/test/CodeGen/X86/build-vector-128.ll60
1 files changed, 30 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/X86/build-vector-128.ll b/llvm/test/CodeGen/X86/build-vector-128.ll
index 384c0828dc6..da92fe6c3fd 100644
--- a/llvm/test/CodeGen/X86/build-vector-128.ll
+++ b/llvm/test/CodeGen/X86/build-vector-128.ll
@@ -10,22 +10,22 @@
define <2 x double> @test_buildvector_v2f64(double %a0, double %a1) {
; SSE-32-LABEL: test_buildvector_v2f64:
-; SSE-32: # BB#0:
+; SSE-32: # %bb.0:
; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0
; SSE-32-NEXT: retl
;
; SSE-64-LABEL: test_buildvector_v2f64:
-; SSE-64: # BB#0:
+; SSE-64: # %bb.0:
; SSE-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-64-NEXT: retq
;
; AVX-32-LABEL: test_buildvector_v2f64:
-; AVX-32: # BB#0:
+; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
; AVX-32-NEXT: retl
;
; AVX-64-LABEL: test_buildvector_v2f64:
-; AVX-64: # BB#0:
+; AVX-64: # %bb.0:
; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-64-NEXT: retq
%ins0 = insertelement <2 x double> undef, double %a0, i32 0
@@ -35,31 +35,31 @@ define <2 x double> @test_buildvector_v2f64(double %a0, double %a1) {
define <4 x float> @test_buildvector_v4f32(float %a0, float %a1, float %a2, float %a3) {
; SSE-32-LABEL: test_buildvector_v4f32:
-; SSE-32: # BB#0:
+; SSE-32: # %bb.0:
; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0
; SSE-32-NEXT: retl
;
; SSE2-64-LABEL: test_buildvector_v4f32:
-; SSE2-64: # BB#0:
+; SSE2-64: # %bb.0:
; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-64-NEXT: retq
;
; SSE41-64-LABEL: test_buildvector_v4f32:
-; SSE41-64: # BB#0:
+; SSE41-64: # %bb.0:
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; SSE41-64-NEXT: retq
;
; AVX-32-LABEL: test_buildvector_v4f32:
-; AVX-32: # BB#0:
+; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
; AVX-32-NEXT: retl
;
; AVX-64-LABEL: test_buildvector_v4f32:
-; AVX-64: # BB#0:
+; AVX-64: # %bb.0:
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
@@ -73,24 +73,24 @@ define <4 x float> @test_buildvector_v4f32(float %a0, float %a1, float %a2, floa
define <2 x i64> @test_buildvector_v2i64(i64 %a0, i64 %a1) {
; SSE-32-LABEL: test_buildvector_v2i64:
-; SSE-32: # BB#0:
+; SSE-32: # %bb.0:
; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0
; SSE-32-NEXT: retl
;
; SSE-64-LABEL: test_buildvector_v2i64:
-; SSE-64: # BB#0:
+; SSE-64: # %bb.0:
; SSE-64-NEXT: movq %rsi, %xmm1
; SSE-64-NEXT: movq %rdi, %xmm0
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-64-NEXT: retq
;
; AVX-32-LABEL: test_buildvector_v2i64:
-; AVX-32: # BB#0:
+; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
; AVX-32-NEXT: retl
;
; AVX-64-LABEL: test_buildvector_v2i64:
-; AVX-64: # BB#0:
+; AVX-64: # %bb.0:
; AVX-64-NEXT: vmovq %rsi, %xmm0
; AVX-64-NEXT: vmovq %rdi, %xmm1
; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
@@ -102,12 +102,12 @@ define <2 x i64> @test_buildvector_v2i64(i64 %a0, i64 %a1) {
define <4 x i32> @test_buildvector_v4i32(i32 %f0, i32 %f1, i32 %f2, i32 %f3) {
; SSE-32-LABEL: test_buildvector_v4i32:
-; SSE-32: # BB#0:
+; SSE-32: # %bb.0:
; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0
; SSE-32-NEXT: retl
;
; SSE2-64-LABEL: test_buildvector_v4i32:
-; SSE2-64: # BB#0:
+; SSE2-64: # %bb.0:
; SSE2-64-NEXT: movd %ecx, %xmm0
; SSE2-64-NEXT: movd %edx, %xmm1
; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
@@ -118,7 +118,7 @@ define <4 x i32> @test_buildvector_v4i32(i32 %f0, i32 %f1, i32 %f2, i32 %f3) {
; SSE2-64-NEXT: retq
;
; SSE41-64-LABEL: test_buildvector_v4i32:
-; SSE41-64: # BB#0:
+; SSE41-64: # %bb.0:
; SSE41-64-NEXT: movd %edi, %xmm0
; SSE41-64-NEXT: pinsrd $1, %esi, %xmm0
; SSE41-64-NEXT: pinsrd $2, %edx, %xmm0
@@ -126,12 +126,12 @@ define <4 x i32> @test_buildvector_v4i32(i32 %f0, i32 %f1, i32 %f2, i32 %f3) {
; SSE41-64-NEXT: retq
;
; AVX-32-LABEL: test_buildvector_v4i32:
-; AVX-32: # BB#0:
+; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
; AVX-32-NEXT: retl
;
; AVX-64-LABEL: test_buildvector_v4i32:
-; AVX-64: # BB#0:
+; AVX-64: # %bb.0:
; AVX-64-NEXT: vmovd %edi, %xmm0
; AVX-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
; AVX-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
@@ -146,7 +146,7 @@ define <4 x i32> @test_buildvector_v4i32(i32 %f0, i32 %f1, i32 %f2, i32 %f3) {
define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) {
; SSE2-32-LABEL: test_buildvector_v8i16:
-; SSE2-32: # BB#0:
+; SSE2-32: # %bb.0:
; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
@@ -165,7 +165,7 @@ define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16
; SSE2-32-NEXT: retl
;
; SSE2-64-LABEL: test_buildvector_v8i16:
-; SSE2-64: # BB#0:
+; SSE2-64: # %bb.0:
; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
@@ -184,7 +184,7 @@ define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16
; SSE2-64-NEXT: retq
;
; SSE41-32-LABEL: test_buildvector_v8i16:
-; SSE41-32: # BB#0:
+; SSE41-32: # %bb.0:
; SSE41-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE41-32-NEXT: pinsrw $1, {{[0-9]+}}(%esp), %xmm0
; SSE41-32-NEXT: pinsrw $2, {{[0-9]+}}(%esp), %xmm0
@@ -196,7 +196,7 @@ define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16
; SSE41-32-NEXT: retl
;
; SSE41-64-LABEL: test_buildvector_v8i16:
-; SSE41-64: # BB#0:
+; SSE41-64: # %bb.0:
; SSE41-64-NEXT: movd %edi, %xmm0
; SSE41-64-NEXT: pinsrw $1, %esi, %xmm0
; SSE41-64-NEXT: pinsrw $2, %edx, %xmm0
@@ -208,7 +208,7 @@ define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16
; SSE41-64-NEXT: retq
;
; AVX-32-LABEL: test_buildvector_v8i16:
-; AVX-32: # BB#0:
+; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
@@ -220,7 +220,7 @@ define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16
; AVX-32-NEXT: retl
;
; AVX-64-LABEL: test_buildvector_v8i16:
-; AVX-64: # BB#0:
+; AVX-64: # %bb.0:
; AVX-64-NEXT: vmovd %edi, %xmm0
; AVX-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0
; AVX-64-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0
@@ -243,7 +243,7 @@ define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16
define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) {
; SSE2-32-LABEL: test_buildvector_v16i8:
-; SSE2-32: # BB#0:
+; SSE2-32: # %bb.0:
; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
@@ -278,7 +278,7 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
; SSE2-32-NEXT: retl
;
; SSE2-64-LABEL: test_buildvector_v16i8:
-; SSE2-64: # BB#0:
+; SSE2-64: # %bb.0:
; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
@@ -313,7 +313,7 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
; SSE2-64-NEXT: retq
;
; SSE41-32-LABEL: test_buildvector_v16i8:
-; SSE41-32: # BB#0:
+; SSE41-32: # %bb.0:
; SSE41-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE41-32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
; SSE41-32-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0
@@ -333,7 +333,7 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
; SSE41-32-NEXT: retl
;
; SSE41-64-LABEL: test_buildvector_v16i8:
-; SSE41-64: # BB#0:
+; SSE41-64: # %bb.0:
; SSE41-64-NEXT: movd %edi, %xmm0
; SSE41-64-NEXT: pinsrb $1, %esi, %xmm0
; SSE41-64-NEXT: pinsrb $2, %edx, %xmm0
@@ -353,7 +353,7 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
; SSE41-64-NEXT: retq
;
; AVX-32-LABEL: test_buildvector_v16i8:
-; AVX-32: # BB#0:
+; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
@@ -373,7 +373,7 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
; AVX-32-NEXT: retl
;
; AVX-64-LABEL: test_buildvector_v16i8:
-; AVX-64: # BB#0:
+; AVX-64: # %bb.0:
; AVX-64-NEXT: vmovd %edi, %xmm0
; AVX-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0
; AVX-64-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0
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