diff options
Diffstat (limited to 'llvm/test/CodeGen/WebAssembly/simd-arith.ll')
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/simd-arith.ll | 168 |
1 files changed, 168 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll index f3e70156d8b..973f78b30dc 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll @@ -765,6 +765,90 @@ define <4 x float> @abs_v4f32(<4 x float> %x) { ret <4 x float> %a } +; CHECK-LABEL: min_unordered_v4f32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <4 x float> @min_unordered_v4f32(<4 x float> %x) { + %cmps = fcmp ule <4 x float> %x, <float 5., float 5., float 5., float 5.> + %a = select <4 x i1> %cmps, <4 x float> %x, + <4 x float> <float 5., float 5., float 5., float 5.> + ret <4 x float> %a +} + +; CHECK-LABEL: max_unordered_v4f32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <4 x float> @max_unordered_v4f32(<4 x float> %x) { + %cmps = fcmp uge <4 x float> %x, <float 5., float 5., float 5., float 5.> + %a = select <4 x i1> %cmps, <4 x float> %x, + <4 x float> <float 5., float 5., float 5., float 5.> + ret <4 x float> %a +} + +; CHECK-LABEL: min_ordered_v4f32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <4 x float> @min_ordered_v4f32(<4 x float> %x) { + %cmps = fcmp ole <4 x float> <float 5., float 5., float 5., float 5.>, %x + %a = select <4 x i1> %cmps, + <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x + ret <4 x float> %a +} + +; CHECK-LABEL: max_ordered_v4f32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <4 x float> @max_ordered_v4f32(<4 x float> %x) { + %cmps = fcmp oge <4 x float> <float 5., float 5., float 5., float 5.>, %x + %a = select <4 x i1> %cmps, + <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x + ret <4 x float> %a +} + +; CHECK-LABEL: min_intrinsic_v4f32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128, v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) +define <4 x float> @min_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { + %a = call <4 x float> @llvm.minimum.v4f32(<4 x float> %x, <4 x float> %y) + ret <4 x float> %a +} + +; CHECK-LABEL: max_intrinsic_v4f32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128, v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) +define <4 x float> @max_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { + %a = call <4 x float> @llvm.maximum.v4f32(<4 x float> %x, <4 x float> %y) + ret <4 x float> %a +} + ; CHECK-LABEL: add_v4f32: ; NO-SIMD128-NOT: f32x4 ; SIMD128-NEXT: .param v128, v128{{$}} @@ -848,6 +932,90 @@ define <2 x double> @abs_v2f64(<2 x double> %x) { ret <2 x double> %a } +; CHECK-LABEL: min_unordered_v2f64: +; NO-SIMD128-NOT: f64x2 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <2 x double> @min_unordered_v2f64(<2 x double> %x) { + %cmps = fcmp ule <2 x double> %x, <double 5., double 5.> + %a = select <2 x i1> %cmps, <2 x double> %x, + <2 x double> <double 5., double 5.> + ret <2 x double> %a +} + +; CHECK-LABEL: max_unordered_v2f64: +; NO-SIMD128-NOT: f64x2 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <2 x double> @max_unordered_v2f64(<2 x double> %x) { + %cmps = fcmp uge <2 x double> %x, <double 5., double 5.> + %a = select <2 x i1> %cmps, <2 x double> %x, + <2 x double> <double 5., double 5.> + ret <2 x double> %a +} + +; CHECK-LABEL: min_ordered_v2f64: +; NO-SIMD128-NOT: f64x2 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <2 x double> @min_ordered_v2f64(<2 x double> %x) { + %cmps = fcmp ole <2 x double> <double 5., double 5.>, %x + %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, + <2 x double> %x + ret <2 x double> %a +} + +; CHECK-LABEL: max_ordered_v2f64: +; NO-SIMD128-NOT: f64x2 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 +; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] +; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +define <2 x double> @max_ordered_v2f64(<2 x double> %x) { + %cmps = fcmp oge <2 x double> <double 5., double 5.>, %x + %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, + <2 x double> %x + ret <2 x double> %a +} + +; CHECK-LABEL: min_intrinsic_v2f64: +; NO-SIMD128-NOT: f64x2 +; SIMD128-NEXT: .param v128, v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $1{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) +define <2 x double> @min_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { + %a = call <2 x double> @llvm.minimum.v2f64(<2 x double> %x, <2 x double> %y) + ret <2 x double> %a +} + +; CHECK-LABEL: max_intrinsic_v2f64: +; NO-SIMD128-NOT: f64x2 +; SIMD128-NEXT: .param v128, v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $1{{$}} +; SIMD128-NEXT: return $pop[[R]]{{$}} +declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) +define <2 x double> @max_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { + %a = call <2 x double> @llvm.maximum.v2f64(<2 x double> %x, <2 x double> %y) + ret <2 x double> %a +} + ; CHECK-LABEL: add_v2f64: ; NO-SIMD128-NOT: f64x2 ; SIMD128-VM-NOT: f62x2 |
