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Diffstat (limited to 'llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll')
-rw-r--r--llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll170
1 files changed, 79 insertions, 91 deletions
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
index b8b518c471e..5be074d298f 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
@@ -6,13 +6,12 @@ define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-LABEL: build_var0_v4i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #0, #4
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #0, #4
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -26,13 +25,12 @@ define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-LABEL: build_var3_v4i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #12, #4
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #12, #4
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -46,16 +44,15 @@ define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-LABEL: build_varN_v4i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #0, #4
-; CHECK-NEXT: bfi r2, r0, #4, #4
-; CHECK-NEXT: bfi r2, r0, #8, #4
-; CHECK-NEXT: bfi r2, r0, #12, #4
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #0, #4
+; CHECK-NEXT: bfi r1, r0, #4, #4
+; CHECK-NEXT: bfi r1, r0, #8, #4
+; CHECK-NEXT: bfi r1, r0, #12, #4
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -71,13 +68,12 @@ define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-LABEL: build_var0_v8i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #0, #2
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #0, #2
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -91,13 +87,12 @@ define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-LABEL: build_var3_v8i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #6, #2
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #6, #2
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -111,20 +106,19 @@ define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-LABEL: build_varN_v8i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #0, #2
-; CHECK-NEXT: bfi r2, r0, #2, #2
-; CHECK-NEXT: bfi r2, r0, #4, #2
-; CHECK-NEXT: bfi r2, r0, #6, #2
-; CHECK-NEXT: bfi r2, r0, #8, #2
-; CHECK-NEXT: bfi r2, r0, #10, #2
-; CHECK-NEXT: bfi r2, r0, #12, #2
-; CHECK-NEXT: bfi r2, r0, #14, #2
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #0, #2
+; CHECK-NEXT: bfi r1, r0, #2, #2
+; CHECK-NEXT: bfi r1, r0, #4, #2
+; CHECK-NEXT: bfi r1, r0, #6, #2
+; CHECK-NEXT: bfi r1, r0, #8, #2
+; CHECK-NEXT: bfi r1, r0, #10, #2
+; CHECK-NEXT: bfi r1, r0, #12, #2
+; CHECK-NEXT: bfi r1, r0, #14, #2
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -140,13 +134,12 @@ define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-LABEL: build_var0_v16i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #0, #1
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #0, #1
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -160,13 +153,12 @@ define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-LABEL: build_var3_v16i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #3, #1
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #3, #1
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -180,28 +172,27 @@ define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-LABEL: build_varN_v16i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r0, #1
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov.w r1, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: bfi r2, r0, #0, #1
-; CHECK-NEXT: bfi r2, r0, #1, #1
-; CHECK-NEXT: bfi r2, r0, #2, #1
-; CHECK-NEXT: bfi r2, r0, #3, #1
-; CHECK-NEXT: bfi r2, r0, #4, #1
-; CHECK-NEXT: bfi r2, r0, #5, #1
-; CHECK-NEXT: bfi r2, r0, #6, #1
-; CHECK-NEXT: bfi r2, r0, #7, #1
-; CHECK-NEXT: bfi r2, r0, #8, #1
-; CHECK-NEXT: bfi r2, r0, #9, #1
-; CHECK-NEXT: bfi r2, r0, #10, #1
-; CHECK-NEXT: bfi r2, r0, #11, #1
-; CHECK-NEXT: bfi r2, r0, #12, #1
-; CHECK-NEXT: bfi r2, r0, #13, #1
-; CHECK-NEXT: bfi r2, r0, #14, #1
-; CHECK-NEXT: bfi r2, r0, #15, #1
-; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: bfi r1, r0, #0, #1
+; CHECK-NEXT: bfi r1, r0, #1, #1
+; CHECK-NEXT: bfi r1, r0, #2, #1
+; CHECK-NEXT: bfi r1, r0, #3, #1
+; CHECK-NEXT: bfi r1, r0, #4, #1
+; CHECK-NEXT: bfi r1, r0, #5, #1
+; CHECK-NEXT: bfi r1, r0, #6, #1
+; CHECK-NEXT: bfi r1, r0, #7, #1
+; CHECK-NEXT: bfi r1, r0, #8, #1
+; CHECK-NEXT: bfi r1, r0, #9, #1
+; CHECK-NEXT: bfi r1, r0, #10, #1
+; CHECK-NEXT: bfi r1, r0, #11, #1
+; CHECK-NEXT: bfi r1, r0, #12, #1
+; CHECK-NEXT: bfi r1, r0, #13, #1
+; CHECK-NEXT: bfi r1, r0, #14, #1
+; CHECK-NEXT: bfi r1, r0, #15, #1
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@@ -216,11 +207,10 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var0_v2i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r2, #1
-; CHECK-NEXT: rsbs r0, r2, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
+; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vldr s10, .LCPI9_0
; CHECK-NEXT: vmov.f32 s9, s8
@@ -243,11 +233,10 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var1_v2i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r2, #1
-; CHECK-NEXT: rsbs r0, r2, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
+; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vldr s8, .LCPI10_0
; CHECK-NEXT: vmov.f32 s9, s8
@@ -270,11 +259,10 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_varN_v2i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: it lo
-; CHECK-NEXT: movlo r2, #1
-; CHECK-NEXT: rsbs r0, r2, #0
+; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: and r0, r0, #1
+; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2
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