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-rw-r--r--llvm/test/CodeGen/RISCV/analyze-branch.ll6
-rw-r--r--llvm/test/CodeGen/RISCV/branch-relaxation.ll79
-rw-r--r--llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll36
-rw-r--r--llvm/test/CodeGen/RISCV/jumptable.ll20
4 files changed, 110 insertions, 31 deletions
diff --git a/llvm/test/CodeGen/RISCV/analyze-branch.ll b/llvm/test/CodeGen/RISCV/analyze-branch.ll
index eb370e7d06f..0a6411282d0 100644
--- a/llvm/test/CodeGen/RISCV/analyze-branch.ll
+++ b/llvm/test/CodeGen/RISCV/analyze-branch.ll
@@ -58,8 +58,8 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
-; RV32I-NEXT: beq a0, a1, .LBB1_1
-; RV32I-NEXT: # %bb.3: # %false
+; RV32I-NEXT: beq a0, a1, .LBB1_3
+; RV32I-NEXT: # %bb.1: # %false
; RV32I-NEXT: lui a0, %hi(test_false)
; RV32I-NEXT: addi a0, a0, %lo(test_false)
; RV32I-NEXT: .LBB1_2: # %true
@@ -68,7 +68,7 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB1_1: # %true
+; RV32I-NEXT: .LBB1_3: # %true
; RV32I-NEXT: lui a0, %hi(test_true)
; RV32I-NEXT: addi a0, a0, %lo(test_true)
; RV32I-NEXT: j .LBB1_2
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation.ll b/llvm/test/CodeGen/RISCV/branch-relaxation.ll
new file mode 100644
index 00000000000..5c66d1d6798
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -filetype=obj < %s \
+; RUN: -o /dev/null 2>&1
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
+
+define void @relax_bcc(i1 %a) {
+; CHECK-LABEL: relax_bcc:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sw ra, 12(sp)
+; CHECK-NEXT: sw s0, 8(sp)
+; CHECK-NEXT: addi s0, sp, 16
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: bnez a0, .LBB0_1
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_1: # %iftrue
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .space 4096
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB0_2: # %tail
+; CHECK-NEXT: lw s0, 8(sp)
+; CHECK-NEXT: lw ra, 12(sp)
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ br i1 %a, label %iftrue, label %tail
+
+iftrue:
+ call void asm sideeffect ".space 4096", ""()
+ br label %tail
+
+tail:
+ ret void
+}
+
+define i32 @relax_jal(i1 %a) {
+; CHECK-LABEL: relax_jal:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sw ra, 12(sp)
+; CHECK-NEXT: sw s0, 8(sp)
+; CHECK-NEXT: addi s0, sp, 16
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: bnez a0, .LBB1_1
+; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: lui a0, %hi(.LBB1_2)
+; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2)
+; CHECK-NEXT: .LBB1_1: # %iftrue
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .space 1048576
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: j .LBB1_3
+; CHECK-NEXT: .LBB1_2: # %jmp
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB1_3: # %tail
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: lw s0, 8(sp)
+; CHECK-NEXT: lw ra, 12(sp)
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ br i1 %a, label %iftrue, label %jmp
+
+jmp:
+ call void asm sideeffect "", ""()
+ br label %tail
+
+iftrue:
+ call void asm sideeffect "", ""()
+ br label %space
+
+space:
+ call void asm sideeffect ".space 1048576", ""()
+ br label %tail
+
+tail:
+ ret i32 1
+}
diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index b73149105ea..47933d699d2 100644
--- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -108,8 +108,8 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a1, a0, 255
-; RV32I-NEXT: beqz a1, .LBB3_1
-; RV32I-NEXT: # %bb.2: # %cond.false
+; RV32I-NEXT: beqz a1, .LBB3_2
+; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
@@ -136,7 +136,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB3_3
-; RV32I-NEXT: .LBB3_1:
+; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
@@ -157,8 +157,8 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
-; RV32I-NEXT: beqz a1, .LBB4_1
-; RV32I-NEXT: # %bb.2: # %cond.false
+; RV32I-NEXT: beqz a1, .LBB4_2
+; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
@@ -185,7 +185,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB4_3
-; RV32I-NEXT: .LBB4_1:
+; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
@@ -203,8 +203,8 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: beqz a0, .LBB5_1
-; RV32I-NEXT: # %bb.2: # %cond.false
+; RV32I-NEXT: beqz a0, .LBB5_2
+; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
@@ -231,7 +231,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB5_3
-; RV32I-NEXT: .LBB5_1:
+; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
@@ -249,8 +249,8 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: beqz a0, .LBB6_1
-; RV32I-NEXT: # %bb.2: # %cond.false
+; RV32I-NEXT: beqz a0, .LBB6_2
+; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 2
@@ -285,7 +285,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB6_3
-; RV32I-NEXT: .LBB6_1:
+; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
@@ -354,12 +354,12 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
-; RV32I-NEXT: bnez s3, .LBB7_1
-; RV32I-NEXT: # %bb.2:
+; RV32I-NEXT: bnez s3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3
-; RV32I-NEXT: .LBB7_1:
+; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
@@ -557,12 +557,12 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
-; RV32I-NEXT: bnez s3, .LBB11_1
-; RV32I-NEXT: # %bb.2:
+; RV32I-NEXT: bnez s3, .LBB11_2
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3
-; RV32I-NEXT: .LBB11_1:
+; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll
index 678aca5c8d0..ba545f8797e 100644
--- a/llvm/test/CodeGen/RISCV/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable.ll
@@ -13,30 +13,30 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: blt a2, a0, .LBB0_4
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: addi a3, zero, 1
-; RV32I-NEXT: beq a0, a3, .LBB0_8
+; RV32I-NEXT: beq a0, a3, .LBB0_7
; RV32I-NEXT: # %bb.2: # %entry
-; RV32I-NEXT: bne a0, a2, .LBB0_10
+; RV32I-NEXT: bne a0, a2, .LBB0_9
; RV32I-NEXT: # %bb.3: # %bb2
; RV32I-NEXT: addi a0, zero, 3
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: j .LBB0_10
+; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_4: # %entry
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: beq a0, a3, .LBB0_9
+; RV32I-NEXT: beq a0, a3, .LBB0_8
; RV32I-NEXT: # %bb.5: # %entry
; RV32I-NEXT: addi a2, zero, 4
-; RV32I-NEXT: bne a0, a2, .LBB0_10
+; RV32I-NEXT: bne a0, a2, .LBB0_9
; RV32I-NEXT: # %bb.6: # %bb4
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: j .LBB0_10
-; RV32I-NEXT: .LBB0_8: # %bb1
+; RV32I-NEXT: j .LBB0_9
+; RV32I-NEXT: .LBB0_7: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: j .LBB0_10
-; RV32I-NEXT: .LBB0_9: # %bb3
+; RV32I-NEXT: j .LBB0_9
+; RV32I-NEXT: .LBB0_8: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
-; RV32I-NEXT: .LBB0_10: # %exit
+; RV32I-NEXT: .LBB0_9: # %exit
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
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