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-rw-r--r--llvm/test/CodeGen/RISCV/mem.ll21
1 files changed, 8 insertions, 13 deletions
diff --git a/llvm/test/CodeGen/RISCV/mem.ll b/llvm/test/CodeGen/RISCV/mem.ll
index 60c19dea10f..f157b230fa8 100644
--- a/llvm/test/CodeGen/RISCV/mem.ll
+++ b/llvm/test/CodeGen/RISCV/mem.ll
@@ -163,17 +163,14 @@ define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
@G = global i32 0
define i32 @lw_sw_global(i32 %a) nounwind {
-; TODO: the addi should be folded in to the lw/sw operations
; RV32I-LABEL: lw_sw_global:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a1, %hi(G)
-; RV32I-NEXT: addi a2, a1, %lo(G)
-; RV32I-NEXT: lw a1, 0(a2)
-; RV32I-NEXT: sw a0, 0(a2)
+; RV32I-NEXT: lui a2, %hi(G)
+; RV32I-NEXT: lw a1, %lo(G)(a2)
+; RV32I-NEXT: sw a0, %lo(G)(a2)
; RV32I-NEXT: lui a2, %hi(G+36)
-; RV32I-NEXT: addi a2, a2, %lo(G+36)
-; RV32I-NEXT: lw a3, 0(a2)
-; RV32I-NEXT: sw a0, 0(a2)
+; RV32I-NEXT: lw a3, %lo(G+36)(a2)
+; RV32I-NEXT: sw a0, %lo(G+36)(a2)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = load volatile i32, i32* @G
@@ -186,13 +183,11 @@ define i32 @lw_sw_global(i32 %a) nounwind {
; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
define i32 @lw_sw_constant(i32 %a) nounwind {
-; TODO: the addi should be folded in to the lw/sw
; RV32I-LABEL: lw_sw_constant:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a1, 912092
-; RV32I-NEXT: addi a2, a1, -273
-; RV32I-NEXT: lw a1, 0(a2)
-; RV32I-NEXT: sw a0, 0(a2)
+; RV32I-NEXT: lui a2, 912092
+; RV32I-NEXT: lw a1, -273(a2)
+; RV32I-NEXT: sw a0, -273(a2)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = inttoptr i32 3735928559 to i32*
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