| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Switch to the Machine Scheduler | Luis Marques | 2019-09-17 | 1 | -21/+24 |
| * | Revert Patch from Phabricator | Luis Marques | 2019-09-17 | 1 | -24/+21 |
| * | Patch from Phabricator | Luis Marques | 2019-09-17 | 1 | -21/+24 |
| * | [RISCV] Separate base from offset in lowerGlobalAddress | Sameer AbuAsal | 2018-05-17 | 1 | -3/+3 |
| * | [RISCV] Peephole optimisation for load/store of global values or constant add... | Alex Bradbury | 2018-03-19 | 1 | -13/+8 |
| * | [RISCV] Implement frame pointer elimination | Alex Bradbury | 2018-01-18 | 1 | -84/+0 |
| * | [RISCV] Enable emission of alias instructions by default | Alex Bradbury | 2017-12-15 | 1 | -14/+14 |
| * | [RISCV] Implement prolog and epilog insertion | Alex Bradbury | 2017-12-11 | 1 | -0/+84 |
| * | [CodeGen] Unify MBB reference format in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-04 | 1 | -12/+12 |
| * | [RISCV] Codegen support for memory operations on global addresses | Alex Bradbury | 2017-11-08 | 1 | -0/+25 |
| * | [RISCV] Codegen support for memory operations | Alex Bradbury | 2017-11-08 | 1 | -0/+177 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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