1 files changed, 136 insertions, 87 deletions
diff --git a/llvm/test/CodeGen/RISCV/large-stack.ll b/llvm/test/CodeGen/RISCV/large-stack.ll
index 8ee818bed91..51130fc2a94 100644
--- a/llvm/test/CodeGen/RISCV/large-stack.ll
+++ b/llvm/test/CodeGen/RISCV/large-stack.ll
@@ -1,38 +1,50 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN:   | FileCheck -check-prefix=RV32I-FPELIM %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
+; RUN:   | FileCheck -check-prefix=RV32I-WITHFP %s
 
 ; TODO: the quality of the generated code is poor
 
 define void @test() nounwind {
-; RV32I-LABEL: test:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1680
-; RV32I-NEXT:    sub sp, sp, a0
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1676
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    sw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1672
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    sw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1680
-; RV32I-NEXT:    add s0, sp, a0
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1672
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1676
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 74565
-; RV32I-NEXT:    addi a0, a0, 1680
-; RV32I-NEXT:    add sp, sp, a0
-; RV32I-NEXT:    ret
+; RV32I-FPELIM-LABEL: test:
+; RV32I-FPELIM:       # %bb.0:
+; RV32I-FPELIM-NEXT:    lui a0, 74565
+; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
+; RV32I-FPELIM-NEXT:    sub sp, sp, a0
+; RV32I-FPELIM-NEXT:    lui a0, 74565
+; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
+; RV32I-FPELIM-NEXT:    add sp, sp, a0
+; RV32I-FPELIM-NEXT:    ret
+;
+; RV32I-WITHFP-LABEL: test:
+; RV32I-WITHFP:       # %bb.0:
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1680
+; RV32I-WITHFP-NEXT:    sub sp, sp, a0
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1676
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    sw ra, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1672
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    sw s0, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1680
+; RV32I-WITHFP-NEXT:    add s0, sp, a0
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1672
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    lw s0, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1676
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    lw ra, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 74565
+; RV32I-WITHFP-NEXT:    addi a0, a0, 1680
+; RV32I-WITHFP-NEXT:    add sp, sp, a0
+; RV32I-WITHFP-NEXT:    ret
   %tmp = alloca [ 305419896 x i8 ] , align 4
   ret void
 }
@@ -41,64 +53,101 @@ define void @test() nounwind {
 ; use of the emergency spill slot.
 
 define void @test_emergency_spill_slot(i32 %a) nounwind {
-; RV32I-LABEL: test_emergency_spill_slot:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 98
-; RV32I-NEXT:    addi a1, a1, -1376
-; RV32I-NEXT:    sub sp, sp, a1
-; RV32I-NEXT:    lui a1, 98
-; RV32I-NEXT:    addi a1, a1, -1380
-; RV32I-NEXT:    add a1, sp, a1
-; RV32I-NEXT:    sw ra, 0(a1)
-; RV32I-NEXT:    lui a1, 98
-; RV32I-NEXT:    addi a1, a1, -1384
-; RV32I-NEXT:    add a1, sp, a1
-; RV32I-NEXT:    sw s0, 0(a1)
-; RV32I-NEXT:    lui a1, 98
-; RV32I-NEXT:    addi a1, a1, -1388
-; RV32I-NEXT:    add a1, sp, a1
-; RV32I-NEXT:    sw s1, 0(a1)
-; RV32I-NEXT:    lui a1, 98
-; RV32I-NEXT:    addi a1, a1, -1392
-; RV32I-NEXT:    add a1, sp, a1
-; RV32I-NEXT:    sw s2, 0(a1)
-; RV32I-NEXT:    lui a1, 98
-; RV32I-NEXT:    addi a1, a1, -1376
-; RV32I-NEXT:    add s0, sp, a1
-; RV32I-NEXT:    lui a1, 78
-; RV32I-NEXT:    addi a1, a1, 512
-; RV32I-NEXT:    lui a2, 1048478
-; RV32I-NEXT:    addi a2, a2, 1388
-; RV32I-NEXT:    add a2, s0, a2
-; RV32I-NEXT:    mv a2, a2
-; RV32I-NEXT:    add a1, a2, a1
-; RV32I-NEXT:    #APP
-; RV32I-NEXT:    nop
-; RV32I-NEXT:    #NO_APP
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:    #APP
-; RV32I-NEXT:    nop
-; RV32I-NEXT:    #NO_APP
-; RV32I-NEXT:    lui a0, 98
-; RV32I-NEXT:    addi a0, a0, -1392
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw s2, 0(a0)
-; RV32I-NEXT:    lui a0, 98
-; RV32I-NEXT:    addi a0, a0, -1388
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw s1, 0(a0)
-; RV32I-NEXT:    lui a0, 98
-; RV32I-NEXT:    addi a0, a0, -1384
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 98
-; RV32I-NEXT:    addi a0, a0, -1380
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 98
-; RV32I-NEXT:    addi a0, a0, -1376
-; RV32I-NEXT:    add sp, sp, a0
-; RV32I-NEXT:    ret
+; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
+; RV32I-FPELIM:       # %bb.0:
+; RV32I-FPELIM-NEXT:    lui a1, 98
+; RV32I-FPELIM-NEXT:    addi a1, a1, -1392
+; RV32I-FPELIM-NEXT:    sub sp, sp, a1
+; RV32I-FPELIM-NEXT:    lui a1, 98
+; RV32I-FPELIM-NEXT:    addi a1, a1, -1396
+; RV32I-FPELIM-NEXT:    add a1, sp, a1
+; RV32I-FPELIM-NEXT:    sw s1, 0(a1)
+; RV32I-FPELIM-NEXT:    lui a1, 98
+; RV32I-FPELIM-NEXT:    addi a1, a1, -1400
+; RV32I-FPELIM-NEXT:    add a1, sp, a1
+; RV32I-FPELIM-NEXT:    sw s2, 0(a1)
+; RV32I-FPELIM-NEXT:    lui a1, 78
+; RV32I-FPELIM-NEXT:    addi a1, a1, 512
+; RV32I-FPELIM-NEXT:    addi a2, sp, 8
+; RV32I-FPELIM-NEXT:    add a1, a2, a1
+; RV32I-FPELIM-NEXT:    #APP
+; RV32I-FPELIM-NEXT:    nop
+; RV32I-FPELIM-NEXT:    #NO_APP
+; RV32I-FPELIM-NEXT:    sw a0, 0(a1)
+; RV32I-FPELIM-NEXT:    #APP
+; RV32I-FPELIM-NEXT:    nop
+; RV32I-FPELIM-NEXT:    #NO_APP
+; RV32I-FPELIM-NEXT:    lui a0, 98
+; RV32I-FPELIM-NEXT:    addi a0, a0, -1400
+; RV32I-FPELIM-NEXT:    add a0, sp, a0
+; RV32I-FPELIM-NEXT:    lw s2, 0(a0)
+; RV32I-FPELIM-NEXT:    lui a0, 98
+; RV32I-FPELIM-NEXT:    addi a0, a0, -1396
+; RV32I-FPELIM-NEXT:    add a0, sp, a0
+; RV32I-FPELIM-NEXT:    lw s1, 0(a0)
+; RV32I-FPELIM-NEXT:    lui a0, 98
+; RV32I-FPELIM-NEXT:    addi a0, a0, -1392
+; RV32I-FPELIM-NEXT:    add sp, sp, a0
+; RV32I-FPELIM-NEXT:    ret
+;
+; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
+; RV32I-WITHFP:       # %bb.0:
+; RV32I-WITHFP-NEXT:    lui a1, 98
+; RV32I-WITHFP-NEXT:    addi a1, a1, -1376
+; RV32I-WITHFP-NEXT:    sub sp, sp, a1
+; RV32I-WITHFP-NEXT:    lui a1, 98
+; RV32I-WITHFP-NEXT:    addi a1, a1, -1380
+; RV32I-WITHFP-NEXT:    add a1, sp, a1
+; RV32I-WITHFP-NEXT:    sw ra, 0(a1)
+; RV32I-WITHFP-NEXT:    lui a1, 98
+; RV32I-WITHFP-NEXT:    addi a1, a1, -1384
+; RV32I-WITHFP-NEXT:    add a1, sp, a1
+; RV32I-WITHFP-NEXT:    sw s0, 0(a1)
+; RV32I-WITHFP-NEXT:    lui a1, 98
+; RV32I-WITHFP-NEXT:    addi a1, a1, -1388
+; RV32I-WITHFP-NEXT:    add a1, sp, a1
+; RV32I-WITHFP-NEXT:    sw s1, 0(a1)
+; RV32I-WITHFP-NEXT:    lui a1, 98
+; RV32I-WITHFP-NEXT:    addi a1, a1, -1392
+; RV32I-WITHFP-NEXT:    add a1, sp, a1
+; RV32I-WITHFP-NEXT:    sw s2, 0(a1)
+; RV32I-WITHFP-NEXT:    lui a1, 98
+; RV32I-WITHFP-NEXT:    addi a1, a1, -1376
+; RV32I-WITHFP-NEXT:    add s0, sp, a1
+; RV32I-WITHFP-NEXT:    lui a1, 78
+; RV32I-WITHFP-NEXT:    addi a1, a1, 512
+; RV32I-WITHFP-NEXT:    lui a2, 1048478
+; RV32I-WITHFP-NEXT:    addi a2, a2, 1388
+; RV32I-WITHFP-NEXT:    add a2, s0, a2
+; RV32I-WITHFP-NEXT:    mv a2, a2
+; RV32I-WITHFP-NEXT:    add a1, a2, a1
+; RV32I-WITHFP-NEXT:    #APP
+; RV32I-WITHFP-NEXT:    nop
+; RV32I-WITHFP-NEXT:    #NO_APP
+; RV32I-WITHFP-NEXT:    sw a0, 0(a1)
+; RV32I-WITHFP-NEXT:    #APP
+; RV32I-WITHFP-NEXT:    nop
+; RV32I-WITHFP-NEXT:    #NO_APP
+; RV32I-WITHFP-NEXT:    lui a0, 98
+; RV32I-WITHFP-NEXT:    addi a0, a0, -1392
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    lw s2, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 98
+; RV32I-WITHFP-NEXT:    addi a0, a0, -1388
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    lw s1, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 98
+; RV32I-WITHFP-NEXT:    addi a0, a0, -1384
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    lw s0, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 98
+; RV32I-WITHFP-NEXT:    addi a0, a0, -1380
+; RV32I-WITHFP-NEXT:    add a0, sp, a0
+; RV32I-WITHFP-NEXT:    lw ra, 0(a0)
+; RV32I-WITHFP-NEXT:    lui a0, 98
+; RV32I-WITHFP-NEXT:    addi a0, a0, -1376
+; RV32I-WITHFP-NEXT:    add sp, sp, a0
+; RV32I-WITHFP-NEXT:    ret
   %data = alloca [ 100000 x i32 ] , align 4
   %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
   %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()