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-rw-r--r--llvm/test/CodeGen/RISCV/bare-select.ll16
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/RISCV/bare-select.ll b/llvm/test/CodeGen/RISCV/bare-select.ll
index cf8fe96742b..1b8f2f63e99 100644
--- a/llvm/test/CodeGen/RISCV/bare-select.ll
+++ b/llvm/test/CodeGen/RISCV/bare-select.ll
@@ -5,12 +5,12 @@
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a3, a0, 1
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: bnez a3, .LBB0_2
+; RV32I-NEXT: andi a0, a0, 1
+; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: .LBB0_2:
+; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
@@ -19,12 +19,12 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32I-LABEL: bare_select_float:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a3, a0, 1
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: bnez a3, .LBB1_2
+; RV32I-NEXT: andi a0, a0, 1
+; RV32I-NEXT: bnez a0, .LBB1_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
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