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-rw-r--r--llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll b/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
index 7c28df4c30f..068e52f6175 100644
--- a/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
+++ b/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
@@ -4,7 +4,7 @@
; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
-define i64 @addc_adde(i64 %a, i64 %b) {
+define i64 @addc_adde(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: addc_adde:
; RV32I: # %bb.0:
; RV32I-NEXT: add a1, a1, a3
@@ -17,7 +17,7 @@ define i64 @addc_adde(i64 %a, i64 %b) {
ret i64 %1
}
-define i64 @subc_sube(i64 %a, i64 %b) {
+define i64 @subc_sube(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: subc_sube:
; RV32I: # %bb.0:
; RV32I-NEXT: sub a1, a1, a3
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