diff options
Diffstat (limited to 'llvm/test/CodeGen/R600/trunc.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/trunc.ll | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/llvm/test/CodeGen/R600/trunc.ll b/llvm/test/CodeGen/R600/trunc.ll index 16c57f7f386..7519d10f92b 100644 --- a/llvm/test/CodeGen/R600/trunc.ll +++ b/llvm/test/CodeGen/R600/trunc.ll @@ -3,9 +3,9 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { ; SI-LABEL: {{^}}trunc_i64_to_i32_store: -; SI: S_LOAD_DWORD [[SLOAD:s[0-9]+]], s[0:1], 0xb -; SI: V_MOV_B32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]] -; SI: BUFFER_STORE_DWORD [[VLOAD]] +; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb +; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]] +; SI: buffer_store_dword [[VLOAD]] ; EG-LABEL: {{^}}trunc_i64_to_i32_store: ; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 @@ -17,11 +17,11 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { } ; SI-LABEL: {{^}}trunc_load_shl_i64: -; SI-DAG: S_LOAD_DWORDX2 -; SI-DAG: S_LOAD_DWORD [[SREG:s[0-9]+]], -; SI: S_LSHL_B32 [[SHL:s[0-9]+]], [[SREG]], 2 -; SI: V_MOV_B32_e32 [[VSHL:v[0-9]+]], [[SHL]] -; SI: BUFFER_STORE_DWORD [[VSHL]], +; SI-DAG: s_load_dwordx2 +; SI-DAG: s_load_dword [[SREG:s[0-9]+]], +; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2 +; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]] +; SI: buffer_store_dword [[VSHL]], define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { %b = shl i64 %a, 2 %result = trunc i64 %b to i32 @@ -30,12 +30,12 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { } ; SI-LABEL: {{^}}trunc_shl_i64: -; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI: S_LSHL_B64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2 -; SI: S_ADD_U32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], -; SI: S_ADDC_U32 -; SI: V_MOV_B32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] -; SI: BUFFER_STORE_DWORD v[[LO_VREG]], +; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2 +; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], +; SI: s_addc_u32 +; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] +; SI: buffer_store_dword v[[LO_VREG]], define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) { %aa = add i64 %a, 234 ; Prevent shrinking store. %b = shl i64 %aa, 2 @@ -46,8 +46,8 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 } ; SI-LABEL: {{^}}trunc_i32_to_i1: -; SI: V_AND_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI: V_CMP_EQ_I32 +; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI: v_cmp_eq_i32 define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) { %a = load i32 addrspace(1)* %ptr, align 4 %trunc = trunc i32 %a to i1 @@ -57,8 +57,8 @@ define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) { } ; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1: -; SI: V_AND_B32_e64 v{{[0-9]+}}, 1, s{{[0-9]+}} -; SI: V_CMP_EQ_I32 +; SI: v_and_b32_e64 v{{[0-9]+}}, 1, s{{[0-9]+}} +; SI: v_cmp_eq_i32 define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) { %trunc = trunc i32 %a to i1 %result = select i1 %trunc, i32 1, i32 0 |
