diff options
Diffstat (limited to 'llvm/test/CodeGen/R600/or.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/or.ll | 93 |
1 files changed, 60 insertions, 33 deletions
diff --git a/llvm/test/CodeGen/R600/or.ll b/llvm/test/CodeGen/R600/or.ll index 05d1e0f0416..8e985c75cbd 100644 --- a/llvm/test/CodeGen/R600/or.ll +++ b/llvm/test/CodeGen/R600/or.ll @@ -1,13 +1,13 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s -; EG-CHECK-LABEL: @or_v2i32 -; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-LABEL: @or_v2i32 +; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK-LABEL: @or_v2i32 -;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI-LABEL: @or_v2i32 +; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -18,17 +18,17 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) ret void } -; EG-CHECK-LABEL: @or_v4i32 -; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-LABEL: @or_v4i32 +; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK-LABEL: @or_v4i32 -;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI-LABEL: @or_v4i32 +; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -39,16 +39,16 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) ret void } -; SI-CHECK-LABEL: @scalar_or_i32 -; SI-CHECK: S_OR_B32 +; SI-LABEL: @scalar_or_i32 +; SI: S_OR_B32 define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { %or = or i32 %a, %b store i32 %or, i32 addrspace(1)* %out ret void } -; SI-CHECK-LABEL: @vector_or_i32 -; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} +; SI-LABEL: @vector_or_i32 +; SI: V_OR_B32_e32 v{{[0-9]}} define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) { %loada = load i32 addrspace(1)* %a %or = or i32 %loada, %b @@ -56,20 +56,20 @@ define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) ret void } -; EG-CHECK-LABEL: @scalar_or_i64 -; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y -; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z -; SI-CHECK-LABEL: @scalar_or_i64 -; SI-CHECK: S_OR_B64 +; EG-LABEL: @scalar_or_i64 +; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y +; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z +; SI-LABEL: @scalar_or_i64 +; SI: S_OR_B64 define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { %or = or i64 %a, %b store i64 %or, i64 addrspace(1)* %out ret void } -; SI-CHECK-LABEL: @vector_or_i64 -; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} -; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} +; SI-LABEL: @vector_or_i64 +; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: V_OR_B32_e32 v{{[0-9]}} define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %loadb = load i64 addrspace(1)* %a, align 8 @@ -78,12 +78,39 @@ define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add ret void } -; SI-CHECK-LABEL: @scalar_vector_or_i64 -; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} -; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} +; SI-LABEL: @scalar_vector_or_i64 +; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: V_OR_B32_e32 v{{[0-9]}} define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) { %loada = load i64 addrspace(1)* %a %or = or i64 %loada, %b store i64 %or, i64 addrspace(1)* %out ret void } + +; SI-LABEL: @vector_or_i64_loadimm +; SI-DAG: S_MOV_B32 +; SI-DAG: S_MOV_B32 +; SI-DAG: BUFFER_LOAD_DWORDX2 +; SI: V_OR_B32_e32 +; SI: V_OR_B32_e32 +; SI: S_ENDPGM +define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { + %loada = load i64 addrspace(1)* %a, align 8 + %or = or i64 %loada, 22470723082367 + store i64 %or, i64 addrspace(1)* %out + ret void +} + +; FIXME: The or 0 should really be removed. +; SI-LABEL: @vector_or_i64_imm +; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI: V_OR_B32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]] +; SI: V_OR_B32_e32 {{v[0-9]+}}, 0, {{.*}} +; SI: S_ENDPGM +define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { + %loada = load i64 addrspace(1)* %a, align 8 + %or = or i64 %loada, 8 + store i64 %or, i64 addrspace(1)* %out + ret void +} |
