diff options
Diffstat (limited to 'llvm/test/CodeGen/R600/fceil.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/fceil.ll | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/llvm/test/CodeGen/R600/fceil.ll b/llvm/test/CodeGen/R600/fceil.ll index ef89eedf5cd..56dc796bab5 100644 --- a/llvm/test/CodeGen/R600/fceil.ll +++ b/llvm/test/CodeGen/R600/fceil.ll @@ -9,7 +9,7 @@ declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone ; FUNC-LABEL: {{^}}fceil_f32: -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: CEIL {{\*? *}}[[RESULT]] define void @fceil_f32(float addrspace(1)* %out, float %x) { @@ -19,8 +19,8 @@ define void @fceil_f32(float addrspace(1)* %out, float %x) { } ; FUNC-LABEL: {{^}}fceil_v2f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] @@ -31,9 +31,9 @@ define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v3f32: -; FIXME-SI: V_CEIL_F32_e32 -; FIXME-SI: V_CEIL_F32_e32 -; FIXME-SI: V_CEIL_F32_e32 +; FIXME-SI: v_ceil_f32_e32 +; FIXME-SI: v_ceil_f32_e32 +; FIXME-SI: v_ceil_f32_e32 ; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} @@ -47,10 +47,10 @@ define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v4f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] @@ -63,14 +63,14 @@ define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v8f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} ; EG-DAG: CEIL {{\*? *}}[[RESULT1]] @@ -88,22 +88,22 @@ define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v16f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}} |
