diff options
Diffstat (limited to 'llvm/test/CodeGen/R600/add.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/add.ll | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/llvm/test/CodeGen/R600/add.ll b/llvm/test/CodeGen/R600/add.ll index 9bea9be8485..767a6420908 100644 --- a/llvm/test/CodeGen/R600/add.ll +++ b/llvm/test/CodeGen/R600/add.ll @@ -4,9 +4,9 @@ ;FUNC-LABEL: {{^}}test1: ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} ;SI-CHECK-NOT: [[REG]] -;SI-CHECK: BUFFER_STORE_DWORD [[REG]], +;SI-CHECK: buffer_store_dword [[REG]], define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 %a = load i32 addrspace(1)* %in @@ -20,8 +20,8 @@ define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -38,10 +38,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -61,14 +61,14 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { entry: %0 = add <8 x i32> %a, %b @@ -93,22 +93,22 @@ entry: ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { entry: %0 = add <16 x i32> %a, %b @@ -117,8 +117,8 @@ entry: } ; FUNC-LABEL: {{^}}add64: -; SI-CHECK: S_ADD_U32 -; SI-CHECK: S_ADDC_U32 +; SI-CHECK: s_add_u32 +; SI-CHECK: s_addc_u32 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = add i64 %a, %b @@ -126,13 +126,13 @@ entry: ret void } -; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they +; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they ; use VCC. The test is designed so that %a will be stored in an SGPR and ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a ; to a VGPR before doing the add. ; FUNC-LABEL: {{^}}add64_sgpr_vgpr: -; SI-CHECK-NOT: V_ADDC_U32_e32 s +; SI-CHECK-NOT: v_addc_u32_e32 s define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { entry: %0 = load i64 addrspace(1)* %in @@ -143,8 +143,8 @@ entry: ; Test i64 add inside a branch. ; FUNC-LABEL: {{^}}add64_in_branch: -; SI-CHECK: S_ADD_U32 -; SI-CHECK: S_ADDC_U32 +; SI-CHECK: s_add_u32 +; SI-CHECK: s_addc_u32 define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: %0 = icmp eq i64 %a, 0 |
