diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/vselect-constants.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vselect-constants.ll | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vselect-constants.ll b/llvm/test/CodeGen/PowerPC/vselect-constants.ll index 077eb2defc0..5f23c3e40de 100644 --- a/llvm/test/CodeGen/PowerPC/vselect-constants.ll +++ b/llvm/test/CodeGen/PowerPC/vselect-constants.ll @@ -9,7 +9,7 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_C1_or_C2_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha @@ -29,7 +29,7 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_C1_or_C2_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha @@ -46,7 +46,7 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_Cplus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l @@ -60,7 +60,7 @@ define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l @@ -74,7 +74,7 @@ define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_Cminus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha @@ -91,7 +91,7 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l @@ -105,7 +105,7 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_minus1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vsubuwm 3, 4, 3 @@ -118,7 +118,7 @@ define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_minus1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: blr %cond = icmp eq <4 x i32> %x, %y @@ -128,7 +128,7 @@ define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_0_or_minus1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 @@ -140,7 +140,7 @@ define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_0_or_minus1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: xxlnor 34, 34, 34 ; CHECK-NEXT: blr @@ -151,7 +151,7 @@ define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: blr @@ -161,7 +161,7 @@ define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vspltisw 19, 1 ; CHECK-NEXT: xxland 34, 34, 51 @@ -173,7 +173,7 @@ define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_0_or_1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: xxlandc 34, 35, 34 ; CHECK-NEXT: blr @@ -183,7 +183,7 @@ define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_0_or_1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vspltisw 19, 1 ; CHECK-NEXT: xxlnor 0, 34, 34 |
