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-rw-r--r--llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll3
-rw-r--r--llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll9
2 files changed, 8 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
index 100e8b02162..6b0af667ee4 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
@@ -111,7 +111,8 @@ entry:
; The first four arguments are the same in O32/N32/N64.
; The non-variable portion should be unaffected.
-; O32-DAG: sw $4, 4([[R2]])
+; O32-DAG: mtc1 $4, $f0
+; O32-DAG: swc1 $f0, 4([[R2]])
; NEW-DAG: swc1 $f12, 4([[R2]])
; The varargs portion is dumped to stack
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
index 24bb95c7c68..e98a11a8064 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
@@ -125,9 +125,11 @@ entry:
; I've yet to find a reference in the documentation about this but GCC uses up
; the remaining two argument slots in the GPR's first. We'll do the same for
; compatibility.
-; O32-DAG: sw $6, 12([[R1]])
+; O32-DAG: mtc1 $6, $f0
+; O32-DAG: swc1 $f0, 12([[R1]])
; NEW-DAG: swc1 $f14, 12([[R1]])
-; O32-DAG: sw $7, 16([[R1]])
+; O32-DAG: mtc1 $7, $f0
+; O32-DAG: swc1 $f0, 16([[R1]])
; NEW-DAG: swc1 $f15, 16([[R1]])
; O32 is definitely out of registers now and switches to the stack.
@@ -207,5 +209,6 @@ entry:
; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
; aligned and occupying one slot. We'll use GCC's definition.
-; O32-DAG: sw $5, 4([[R2]])
+; O32-DAG: mtc1 $5, $f0
+; O32-DAG: swc1 $f0, 4([[R2]])
; NEW-DAG: swc1 $f13, 4([[R2]])
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